AN975 Datasheet, PDF (7/11 Pages) STMicroelectronics – As part of a process of continuous improvement

UPGRADING FROM ST625X/6XB TO ST625X/6XC
1.2.4 SPI
When the SPI is used in master mode, the SCK pin (PC4) and Sout pin (PC3) work in output
mode and the Sin pin (PC2) in input mode. On ST625X/6XC, the Port C pins used for the SPI
have to be configured in input mode either with or without pull-up. Their reset configuration
doesn’t have to be changed.
To enable the SPI in master mode, the SPCLK bit in the SPI mode control register has to be
set. By setting this bit, the SCK pin (PC4) is automatically configured in output push-pull mode
and the clock is output at the frequency configured in the SPIDIV register. The output of the
SPI data register Sout pin (PC3) is also automatically configured in output push-pull by setting
bit 0 in the MISCR register.
The following is a software example of how to use the SPI in master mode:
.org 080h (or CSEG AT 080H depending on the toolchain)
reset: clr X
clr A
reti
; Exit NMI mode
ldi WDGR, watchtim
ldi OSCR, 00h
ldi DDRC, 00h
ldi ORC, 00h
ldi DRC, 00h
; Load the watchdog
; Set the oscillator ratio to 1
; Port C in reset state
ldi MISCR, 001h
ldi SPIDIV, 048h
ldi SPIMOD, 03Eh
ldi SPIDR, 0AAh
; Enable Sout
; (PC3 is configured in output push-pull)
; Clock ratio = 1 / 9 bits frame
; CPOL = 0 / Filters enabled / SPCLK = 1 / CPHA = 1
; SPSTRT = 1 / SPIN = 1 / SPIE = 0
; (PC4 is configured as output push-pull)
; Load the data to be send
set 7, SPIMOD
loop: jrs 7, SPIMOD, loop
.....
; Enable the transmission (SPIRUN = 1)
; Poll the bit SPIRUN for end of transmission
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