AN2871 Datasheet, PDF (7/25 Pages) STMicroelectronics – This application note is intended for hardware designers

AN2871
On-chip voltage regulator (VREG)
Figure 1.
External NPN ballast connections configuration for
SPC560P60xx/SPC56AP60xx/SPC560P40xx
VDD_HV_REG
SPC56xx
BCTRL
BJT
C_DEC3
VDD_LV_COR
C_DEC2
C_DEC1
Figure 2. External NPN ballast connections configuration for SPC560P50xx
VDD_HV_REG
SPC56xx
BCTRL
BJT
R_B
C_DEC3
VDD_LV_COR
C_DEC2
C_DEC1
2.1.2
Circuit architecture
The VREG circuit is a classic emitter-follower configuration controlled voltage source. The
stabilization of the output voltage is achieved using an external capacitance of several µF
(see Section 4).
The BCTRL (voltage regulator external NPN ballast base control pin) controls the current on
the base of the transistor. Current is increased to raise the voltage on V_DD. Current is
decreased to lower the voltage. The gain of the transistor controls the maximum current
available on V_DD from the supply.
The gain should be high enough to allow start-up and low enough to prevent the VREG
becoming instable.
Doc ID 15304 Rev 3
7/25