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AN2586 Datasheet, PDF (7/28 Pages) STMicroelectronics – Getting started with STM32F10xxx hardware development
AN2586
Power supplies
1.1.2
1.1.3
On packages with 64 pins or less
The VREF+ and VREF- pins are not available, they are internally connected to the ADC
voltage supply (VDDA) and ground (VSSA).
Battery backup
To retain the content of the Backup registers when VDD is turned off, the VBAT pin can be
connected to an optional standby voltage supplied by a battery or another source.
The VBAT pin also powers the RTC unit, allowing the RTC to operate even when the main
digital supply (VDD) is turned off. The switch to the VBAT supply is controlled by the power
down reset (PDR) circuitry embedded in the Reset block.
If no external battery is used in the application, it is highly recommended to connect VBAT
externally to VDD.
Voltage regulator
The voltage regulator is always enabled after reset. It works in three different modes
depending on the application modes.
● in Run mode, the regulator supplies full power to the 1.8 V domain (core, memories and
digital peripherals)
● in Stop mode, the regulator supplies low power to the 1.8 V domain, preserving the
contents of the registers and SRAM
● in Standby mode, the regulator is powered off. The contents of the registers and SRAM
are lost except for those concerned with the Standby circuitry and the Backup domain.
1.2
Power supply schemes
The circuit is powered by a stabilized power supply, VDD.
● Caution:
– If the ADC is used, the VDD range is limited to 2.4 V to 3.6 V
– If the ADC is not used, the VDD range is 2.0 V to 3.6 V
● The VDD pins must be connected to VDD with external decoupling capacitors (one
100 nF Ceramic capacitor for each VDD pin + one Tantalum or Ceramic capacitor (min.
4.7 µF typ.10 µF).
● The VBAT pin can be connected to the external battery (1.8 V < VBAT < 3.6 V). If no
external battery is used, it is recommended to connect this pin to VDD with a 100 nF
external ceramic decoupling capacitor.
● The VDDA pin must be connected to two external decoupling capacitors (100 nF
Ceramic + 1 µF Tantalum or Ceramic).
● The VREF+ pin can be connected to the VDDA external power supply. If a separate,
external reference voltage is applied on VREF+, a 100 nF and a 1 µF capacitors must be
connected on this pin. In all cases, VREF+ must be kept between 2.4 V and VDDA.
● Additional precautions can be taken to filter analog noise:
– VDDA can be connected to VDD through a ferrite bead.
– The VREF+ pin can be connected to VDDA through a resistor (typ. 47 Ω).
Doc ID 13675 Rev 7
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