PSD834F2V Datasheet, PDF (69/89 Pages) STMicroelectronics – Flash PSD, 3.3V Supply, for 8-bit MCUs 2 Mbit 256 Kbit Dual Flash Memories and 64 Kbit SRAM

PSD834F2V
Table 42. DC Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
V_IH
High Level Input Voltage
3.0 V < V_CC < 3.6 V
0.7V_CC
V_CC +0.5
V
V_IL
Low Level Input Voltage
3.0 V < V_CC < 3.6 V
–0.5
0.8
V
V_IH1
Reset High Level Input Voltage
(Note ¹)
0.8V_CC
V_CC +0.5
V
V_IL1
Reset Low Level Input Voltage
(Note ¹)
–0.5
0.2V_CC –0.1 V
V_HYS
Reset Pin Hysteresis
0.3
V
V_LKO
V_CC (min) for Flash Erase and
Program
1.5
2.2
V
V_OL
Output Low Voltage
I_OL = 20 µA, V_CC = 3.0 V
I_OL = 4 mA, V_CC = 3.0 V
0.01
0.1
V
0.15
0.45
V
V_OH
Output High Voltage Except
V_STBY On
I_OH = –20 µA, V_CC = 3.0 V
I_OH = –1 mA, V_CC = 3.0 V
2.9
2.7
2.99
2.8
V
V
V_OH1
Output High Voltage V_STBY On
I_OH1 = 1 µA
V_STBY – 0.8
V
V_STBY SRAM Stand-by Voltage
2.0
V_CC
V
I_STBY
SRAM Stand-by Current
V_CC = 0 V
0.5
1
µA
I_IDLE
Idle Current (VSTBY input)
V_CC > V_STBY
–0.1
0.1
µA
V_DF
SRAM Data Retention Voltage
Only on V_STBY
2
V
I_SB
Stand-by Supply Current
for Power-down Mode
CSI >V_CC –0.3 V (Notes ^2,3)
25
100
µA
I_LI
Input Leakage Current
V_SS < V_IN < V_CC
–1
±0.1
1
µA
I_LO
Output Leakage Current
0.45 < V_IN < V_CC
–10
±5
10
µA
I_CC (DC)
(Note ⁵)
Operating
Supply
Current
PLD Only
PLD_TURBO = Off,
f = 0 MHz (Note ³)
PLD_TURBO = On,
f = 0 MHz
During Flash memory Write/
Flash memory
Erase Only
Read Only, f = 0 MHz
0
µA/PT
200
400
µA/PT
10
25
mA
0
0
mA
SRAM
f = 0 MHz
0
0
mA
PLD AC Adder
note ⁴
I_CC (AC) _{Flash memory AC Adder}
(Note ⁵)
SRAM AC Adder
1.5
2.0
mA/
MHz
0.8
1.5
mA/
MHz
Note: 1. Reset (Reset) has hysteresis. VIL1 is valid at or below 0.2VCC –0.1. VIH1 is valid at or above 0.8VCC .
2. CSI deselected or internal PD is active.
3. PLD is in non-Turbo mode, and none of the inputs are switching.
4. Please see Figure 32 for the PLD current calculation.
5. I_OUT = 0 mA
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