STLC5464 Datasheet, PDF (68/83 Pages) STMicroelectronics – MULTI-HDLCWITH n x 64 SWITCHING MATRIX ASSOCIATED

STLC5464
VIII - INTERNAL REGISTERS (continued)
VIII.22 - Transmit Command / Indicate Register - TCIR (2A)H
bit15
bit8 bit7
bit 0
0 G0 CA2 CA1 CA0 READ 0
0 Nu Nu C6 C5 C4 C3 C2 C1
After reset (00FF)_H
When this register is written by the microprocessor, these different bits mean :
READ : READ C/I MEMORY
READ = 1, READ C/I MEMORY.
READ = 0, WRITE C/I MEMORY.
CA 0/2 : TRANSMIT COMMAND/INDICATE MEMORY ADDRESS
CA 0/2 : These bits define one of eight Command/Indicate Channels.
G0
C6/1
: This bit defines one of two GCI multiplexes.
G0 = 0, TDM4 is selected.
G0 = 1, TDM5 is selected.
: New Primitive to be transmitted
C6 is transmitted first if ANA = 1.
C4 is transmitted first if ANA = 0.
The New Primitive is taken into account by the transmitter after writing bits 8 to 15 (if 8 bit microprocessor).
Transmit Command/Indicate Register (after reading)
bit15
bit8 bit7
bit 0
0 G0 CA2 CA1 CA0 READ Nu Nu PT1 PT0 C6 C5 C4 C3 C2 C1
When this register is read by the microprocessor, these different bits mean :
READ : READ C/I MEMORY
READ = 1, READ C/I MEMORY.
READ = 0, WRITE C/I MEMORY.
CA 0/2 : TRANSMIT C/I ADDRESS
CA 0/2 : These bits define one of eight Command/Indicate Channels.
G0 : This bit defines one of two GCI multiplexes.
G0 = 0, TDM4 is selected.
G0 = 1, TDM5 is selected.
C6/1 : Last Primitive transmitted.
PT0/1 : Status bits
P1
P0
Primitive Status
0
0 Primitive has not been transmitted yet.
0
1 Primitive has been transmitted once.
1
0 Primitive has been transmitted twice.
1
1 Primitive has been transmitted three times or more.
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