STA382BW Datasheet, PDF (66/172 Pages) STMicroelectronics – Sound Terminal® 2.1-channel high-efficiency digital audio system

Register description: New Map
STA382BW
6.17.3
PWM speed mode
Table 46. PWM speed mode
Bit R/W RST
Name
4 R/W 0
PWMS
Description
0: Normal speed (384 kHz) all channels
1: Odd speed (341.3 kHz) all channels. Not suitable for
binary BTL mode.
6.17.4
Zero-crossing enable
Table 47. Zero-crossing enable
Bit R/W RST
Name
Description
6 R/W 0
ZCE
‘1’: Volume adjustment only occurs at digital zero-crossing
‘0’: Volume adjustment occur immediately
The ZCE bit enables zero-crossing adjustment. When volume is adjusted on digital zero-
crossing, no clicks are audible
6.18 Configuration register F (addr 0x16)
6.18.1
6.18.2
D7
EAPD
0
D6
PWDN
1
D5
ECLE
0
D4
LDTE
1
D3
BCLE
1
D2
D1
D0
IDE
Reserved
Reserved
1
Invalid input detect mute enable
Table 48. Invalid input detect mute enable
Bit R/W RST
Name
Description
2
R/W
1
IDE
Setting of 1 enables the automatic invalid input
detect mute
Setting the IDE bit enables this function, which looks at the input I²S data and automatically
mutes if the signals are perceived as invalid.
Binary output mode clock loss detection
Table 49. Binary output mode clock loss detection
Bit R/W RST
Name
Description
3
R/W
1
BCLE
Binary output mode clock loss detection enable
This bit detects loss of input MCLK in binary mode and will output 50% duty cycle.
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Doc ID 022783 Rev 1