STM8L151F3P6 Datasheet, PDF (65/112 Pages) STMicroelectronics – 8-bit ultralow power MCU, up to 8 KB Flash, up to 256 B data EEPROM

STM8L151x2, STM8L151x3
Electrical parameters
Table 24. Current consumption under external reset
Symbol
Parameter
Conditions
Typ
Unit
V_DD = 1.8 V
48
I_DD(RST)
Supply current under
external reset ⁽¹⁾
All pins are externally
tied to V_DD
V_DD = 3 V
76
µA
V_DD = 3.6 V
91
1. All pins except PA0, PB0 and PB4 are floating under reset. PA0, PB0 and PB4 are configured with pull-up under reset.
7.3.4
Clock and timing characteristics
HSE external clock (HSEBYP = 1 in CLK_ECKCR)
Subject to general operating conditions for V_DD and T_A.
Table 25. HSE external clock characteristics
Symbol
Parameter
Conditions
Min
Typ
f_{HSE_ext}
V_HSEH
External clock source
frequency⁽¹⁾
OSC_IN input pin high level
voltage
1
0.7 x V_DD
V_HSEL
OSC_IN input pin low level
voltage
V_SS
OSC_IN input
C_{in(HSE) capacitance(1)}
2.6
I_{LEAK_HSE}
OSC_IN input leakage
current
V_SS < V_IN < V_DD
1. Data guaranteed by Design, not tested in production.
Max
Unit
16
MHz
V_DD
V
0.3 x V_DD
pF
±1
µA
LSE external clock (LSEBYP=1 in CLK_ECKCR)
Subject to general operating conditions for V_DD and T_A.
Table 26. LSE external clock characteristics
Symbol
Parameter
f_{LSE_ext}
External clock source frequency⁽¹⁾
V_LSEH(2)
OSC32_IN input pin high level voltage
V_LSEL(2)
OSC32_IN input pin low level voltage
C_in(LSE)
OSC32_IN input capacitance⁽¹⁾
I_{LEAK_LSE} OSC32_IN input leakage current
1. Data guaranteed by Design, not tested in production.
2. Data based on characterization results, not tested in production.
Min
0.7 x V_DD
V_SS
Typ
32.768
0.6
Max
V_DD
0.3 x V_DD
±1
Unit
kHz
V
pF
µA
Doc ID 018780 Rev 4
65/112