STM32F103RGT6 Datasheet, PDF (65/120 Pages) STMicroelectronics – XL-density performance line ARM-based 32-bit MCU with 768 KB to 1 MB Flash, USB, CAN, 17 timers, 3 ADCs, 13 communication interfaces

STM32F103xF, STM32F103xG
Electrical characteristics
Figure 24. Asynchronous multiplexed PSRAM/NOR read waveforms
t_w(NE)
FSMC_NE
t_{v(NOE_NE)}
t _{h(NE_NOE)}
FSMC_NOE
FSMC_NWE
FSMC_A[25:16]
FSMC_NBL[1:0]
FSMC_AD[15:0]
FSMC_NADV
t _w(NOE)
t_{v(A_NE)}
t_{v(BL_NE)}
Address
NBL
t_{h(A_NOE)}
t_{h(BL_NOE)}
t _{v(A_NE)}
Address
t _{v(NADV_NE)}
t_w(NADV)
t_{su(Data_NE)}
t_{su(Data_NOE)}
Data
t_{h(AD_NADV)}
t_{h(Data_NE)}
t_{h(Data_NOE)}
ai14892b
Table 34. Asynchronous multiplexed PSRAM/NOR read timings⁽¹⁾
Symbol
Parameter
Min
Max
Unit
t_w(NE)
t_{v(NOE_NE)}
t_w(NOE)
t_{h(NE_NOE)}
t_{v(A_NE)}
t_{v(NADV_NE)}
t_w(NADV)
t_{h(AD_NADV)}
FSMC_NE low time
FSMC_NEx low to FSMC_NOE low
FSMC_NOE low time
FSMC_NOE high to FSMC_NE high hold time
FSMC_NEx low to FSMC_A valid
FSMC_NEx low to FSMC_NADV low
FSMC_NADV low time
FSMC_AD (address) valid hold time after
FSMC_NADV high
t_{h(A_NOE)}
Address hold time after FSMC_NOE high
t_{h(BL_NOE)} FSMC_BL hold time after FSMC_NOE high
t_{v(BL_NE)}
FSMC_NEx low to FSMC_BL valid
t_{su(Data_NE)} Data to FSMC_NEx high setup time
t_{su(Data_NOE)} Data to FSMC_NOE high setup time
t_{h(Data_NE)} Data hold time after FSMC_NEx high
t_{h(Data_NOE)} Data hold time after FSMC_NOE high
1. C_L = 15 pF.
7t_HCLK + 0.5 7t_HCLK + 2 ns
3t_HCLK + 0.5 3t_HCLK + 1.5 ns
4t_HCLK – 1 4t_HCLK + 1 ns
0.5
-
ns
-
0
ns
0
1
ns
t_HCLK + 0.5 t_HCLK + 2 ns
t_HCLK
-
ns
t_HCLK -2
0.5
-
ns
-
ns
-
0
ns
4t_HCLK - 0.5
-
ns
4t_HCLK - 1
-
ns
0
-
ns
0
-
ns
Doc ID 16554 Rev 3
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