STGAP1AS Datasheet, PDF (63/70 Pages) STMicroelectronics – Automotive galvanically isolated advanced single gate driver

STGAP1AS
Programming manual
A description of the STATUS3 register bits is provided in Table 53.
Table 53. STATUS3 register description
Name Bit
Fault
Latched
Force
“safe state”
Note
DT_ERR
Deadtime error flag.
4 This bit is forced high when a violation of
internal DT is detected.
Always
No
See details in Section 7.2
on page 26
SPI communication error flag.
It is forced high when the SPI
communication fails cause:
– Wrong CRC check.
SPI_ERR 3 – Wrong number of CK rising edges.
Always
No
-
– Attempt to execute a not-allowed
command.
Attempt to read, write or reset at a not-
available address.
Register or communication error on low
voltage side.
It is forced high when: -
– Programming procedure is not correctly
REGERRL 2 ^performed.
Always
Yes
-
– Isolated interface communication fails.
– An unexpected register value change
occurs in one of the remote registers.
It is latched at power-up/reset also.
VDD overvoltage flag.
OVLOD 1 It is forced high when VDD is over
Always
Yes
-
OVVDDoff threshold.
VDD undervoltage flag.
UVLOD
0
It is forced high when VDD is below VDDon
threshold. It is latched at power-up/reset
Always
Yes
-
also.
9.2.9
TEST1 register (isolated side)
The TEST1 register has the structure of Table 54.
-
-
Default/reset
Bit 7
-
x
Bit 6
-
x
Table 54. TEST1 register
Bit 5
Bit 4
Bit 3
-
GOFFCHK GONCHK
x
0
0
Bit 2
DESCHK
0
Bit 1
SNSCHK
0
Bit 0
RCHK
0
Setting an one check bit of the register enables the respective check mode.
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