M7010R Datasheet, PDF (61/67 Pages) STMicroelectronics – 16K x 68-bit Entry NETWORK SEARCH ENGINE

M7010R
Figure 44. SRAM WRITE Access for One M7010R Device
Cycle 1 Cycle 2 Cycle 3
Cycle 4
Cycle 5
Cycle 6
CLK 2X
PHS_L
CMDV
CMD[1:0]
Write
CMD[8:2]
AB
DQ
Address
x
x
OE_L
0
WE_L
1
ALE_L, CE_L
1
SADR
ACK
z
0
SSV
SSF
0
TLSZ = 00, HLAT = 000, LRAM = 1, LDEV = 1
1
0
0
Address
AI04296
Table 35. SRAM Bus Address Generation
Command SRAM Operation
21
20
19
SEARCH
Read
C8
C7
C6
LEARN
Write
C8
C7
C6
PIO READ
Read
C8
C7
C6
PIO WRITE
Write
C8
C7
C6
Indirect Access
Write/Read
C8
C7
C6
[18:15]
ID[4:0]
ID[4:0]
ID[4:0]
ID[4:0]
ID[4:0]
[14:0]
Index[14:0]
NFA[14:0]
Adr[14:0]
Adr[14:0]
SSR[14:0]
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