ST7260XX Datasheet, PDF (60/139 Pages) STMicroelectronics – Low speed USB 8-bit MCU family with up to 8K Flash

Watchdog timer (WDG)
ST7260xx
Figure 36. Pulse width modulation mode timing example with two output compare
functions⁽¹⁾⁽²⁾
Counter ^{34E2 FFFC FFFD FFFE}
OCMP1
compare2
OLVL2
2ED0 2ED1 2ED2
34E2 FFFC
OLVL1
compare1
OLVL2
compare2
1. OC1R = 2ED0h, OC2R = 34E2, OLVL1 = 0, OLVL2 = 1
2. On timers with only one Output Compare register, a fixed frequency PWM signal can be generated using
the output compare and the counter overflow to define the pulse length.
Pulse width modulation mode
Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency
and pulse length determined by the value of the OC1R and OC2R registers.
Pulse Width Modulation mode uses the complete Output Compare 1 function plus the
OC2R register, and so this functionality can not be used when PWM mode is activated.
In PWM mode, double buffering is implemented on the output compare registers. Any new
values written in the OC1R and OC2R registers are taken into account only at the end of the
PWM period (OC2) to avoid spikes on the PWM output pin (OCMP1).
Procedure
To use Pulse Width Modulation mode:
1. Load the OC2R register with the value corresponding to the period of the signal using
the formula below.
2. Load the OC1R register with the value corresponding to the period of the pulse if
(OLVL1 = 0 and OLVL2 = 1) using the formula in the opposite column.
3. Select the following in the CR1 register:
– Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a
successful comparison with the OC1R register.
– Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a
successful comparison with the OC2R register.
4. Select the following in the CR2 register:
– Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function.
– Set the PWM bit.
– Select the timer clock (CC[1:0]) (see Table 32).
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