TDA7311 Datasheet, PDF (6/11 Pages) STMicroelectronics – SERIAL BUS CONTROLLED AUDIO PROCESSOR

TDA7311
APPLICATION INFORMATION
SERIAL BUS INTERFACE
The serial bus interface is compatible to SPI bus
systems.
During the LOW state of the chip enable signal
(CE) the data on pin DA are clocked into the shift
register at the LOW to HIGH transition of the
clock signal CL.
At the LOW to HIGH transition of the CE signal
the content of the internal shift register is stored
into the addressed latches.
The transmission is separated into bytes with 8 bit
according to the data specification of the audio-
processor. After every byte a positive slope of the
CE signal has to be generated in order to store
the data byte.
A special clock counter enables the latch of the
data byte only, if exactly 8 clocks were present
during the LOW state of the CE signal. This re-
sults in a high immunity against spikes on the
clock line and avoids a storage of wrong databy-
tes.
Figure 1: BUS Timing
Nr.
Clock Frequency
1
CE Lead time
2
Clock High Time
3
Clock Low Time
4
Data Hold Time
5
Data Setup Time
6
Clock Setup Time
7
CE lagtime
8
Clock Hold Time
9
CE High TIme
Parameter
6/11
Min.
4
2
2
1.8
1.8
0
0
6
6
Max.
250
Units
KHz
µs
µs
µs
µs
µs
µs
µs
µs
µs