STV7699 Datasheet, PDF (6/9 Pages) STMicroelectronics – PLASMA DISPLAY PANEL DATA DRIVER

STV7699
AC TIMINGS REQUIREMENTS
(VCC = 4.5V to 5.5V, Tamb = -20 to +85°C, input signals max leading edge & trailing edge (tR, tF) = 10ns)
Symbol
Parameter
Min. Typ. Max. Unit
t_CLK Data Clock Period
50 -
- ns
tWHCLK Duration of clock (CLK) pulse at high level
15 -
- ns
t_WLCLK Duration of clock (CLK) pulse at low level
15 -
- ns
t_SDAT Set-up Time of data input before clock (low to high) transition
0
-
- ns
t_HDAT Hold Time of data input after clock (low to high) transition
15 -
- ns
tDSTB Minimum Delay to latch (STB) after clock (low to high) transition
20 -
- ns
t_STB Latch (STB) Low Level Pulse Duration
10 -
- ns
t_BLK Blanking (BLK) Pulse Duration
100 -
- ns
tPOL Polarity (POL) Pulse Duration
100 -
- ns
t_HIZ High Impedance (HIZ) Pulse Duration
100 -
- ns
t_SFR Set-up Time of Forward/Reverse Signal before Clock (low to high) transition
100 -
- ns
AC TIMING CHARACTERISTICS
(VCC = 5V, VPP = 65V, VSSP = 0V, VSSLOG = 0V, VSSSUB = 0V, Tamb = 25°C, VILMax. = 0.2VCC, VIHMin. = 0.8VCC,
VOH = 4.0V, VOL = 0.4V, CL = 10pF, unless otherwise specified)
Symbol
Parameter
Min. Typ. Max. Unit
t_CLK Data Clock Period
50 -
- ns
tRDAT Logical Data Output Rise Time
- TBD 30 ns
t_FDAT
t_PHL1
tPLH1
Logical Data Output Fall Time
Delay of logic data output (high to low transition) after clock (CLK) transition
Delay of logic data output (low to high transition) after clock (CLK) transition
- TBD 30 ns
- 40 TBD ns
- 40 TBD ns
tPHL2 Delay of power output change (high to low transition) after clock (CLK) transition - TBD 120 ns
t_PLH2 Delay of power output change (low to high transition) after clock (CLK) transition - TBD 120 ns
t_PHL3 Delay of power output change (high to low transition) after Latch (STB) transition - TBD 110 ns
t_PLH3 Delay of power output change (low to high transition) after Latch (STB) transition - TBD 110 ns
t_PHL4 Delay of power output change (high to low transition) to Blank (BLK) or Polarity - TBD 100 ns
(POL) transition
t_PLH4 Delay of power output change (low to high transition) to Blank (BLK) or Polarity - TBD 100 ns
(POL) transition
t_PHZ5 Delay of power output change (high to Hi-Z transition) after high impedance (HIZ) (5) - TBD 100 ns
tPLZ5 Delay of power output change (low to Hi-Z transition) after high impedance (HIZ) (5) - TBD 100 ns
t_PZH5 Delay of power output change (Hi-Z to high transition) after high impedance (HIZ) (5) - TBD 100 ns
t_PZL5 Delay of power output change (Hi-Z to low transition) after high impedance (HIZ) (5) - TBD 100 ns
tROUT Power Output Rise Time (6)
-
- 150 ns
t_FOUT Power Output Fall Time (6)
-
- 150 ns
Notes : 5. See test diagram.
6. One output among 64, loading capacitor COUT = 50pF, other outputs at low level.
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