M95256_08 Datasheet, PDF (6/43 Pages) STMicroelectronics – 256 Kbit serial SPI bus EEPROM with high-speed clock

Description
1
Description
M95256, M95256-W, M95256-R
The M95256, M95256-W and M95256-R are electrically erasable programmable memory
(EEPROM) devices. They are accessed by a high speed SPI-compatible bus. Their memory
array is organized as 32768 x 8 bits.
The device is accessed by a simple serial interface that is SPI-compatible. The bus signals
are C, D and Q, as shown in Table 1 and Figure 1.
The device is selected when Chip Select (S) is taken low. Communications with the device
can be interrupted using Hold (HOLD).
Figure 1. Logic diagram
VCC
D
C
S
W
HOLD
Q
M95256
VSS
AI12361
Figure 2. SO and TSSOP connections
M95256
S1
Q2
W3
VSS 4
8 VCC
7 HOLD
6C
5D
AI12362
1. See Section 10: Package mechanical data for package dimensions, and how to identify pin-1.
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