M65KG512AB Datasheet, PDF (6/54 Pages) STMicroelectronics – 512Mbit (4 banks x 8 Mb x 16) 1.8 V supply, DDR low power SDRAM

Description
1
Description
M65KG526AB
The M65KG512AB is a 512Mbit Double Data Rate (DDR) Low Power Synchronous DRAM
(LPSDRAM). The memory array is organized as 4 Banks of 8,388,608 words of 16 bits
each.
The device achieves low power consumption and very high-speed data transfer using the 2-
bit prefetch pipeline architecture that allows doubling the data input/output rate. Command
and address inputs are synchronized with the rising edge of the clock while data
inputs/outputs are transferred on both edges of the system clock. The M65KG512AB is well
suited for handheld battery powered applications like PDAs, 2.5 and 3G mobile phones and
handheld computers.
The device architecture is illustrated in Figure 2: Functional block diagram. It uses Burst
mode to read and write data. It is capable of two, four, and eight-word, sequential and
interleaved burst.
To minimize current consumption during self refresh operations, the M65KG512AB includes
three mechanisms configured via the Extended Mode Register:
● Automatic Temperature Compensated Self Refresh (ATCSR) adapts the refresh
frequency according to the operating temperature provided by a built-in temperature
sensor.
● Partial Array Self Refresh (PASR) performs a limited refresh of a half bank, a quarter of
bank, one bank, two banks or all banks.
● The Deep Power-Down (DPD) mode completely halts the refresh operation and
achieves minimum current consumption by cutting off the supply voltage from the
whole memory array.
The device is programmable through two registers, the Mode Register and the Extended
Mode Register:
● The Mode Register is used to select the CAS Latency, the Burst Type (sequential,
interleaved) and the Burst Length. For more details, refer to Table 7: Mode Register
definition, and to Section 3.1: Mode Register Set command (MRS).
● Partial Array Self Refresh (PASR) performs a limited refresh of a half bank, a quarter of
bank, one bank, two banks or all banks.
● The Extended Mode Register is used to configure the low-power features (PASR,
ATCSR and Driver Strength) to reduce the current consumption during the Self Refresh
operations. For more details, refer to Table 8: Extended Mode Register definition, and
to Section 3.2: Extended Mode Register Set command (EMRS).
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