EVAL6520-1421 Datasheet, PDF (6/16 Pages) STMicroelectronics – Standard form factor

Board description
EVAL6520-1421
With these constraints the following is obtained:
Equation 6
Vbe
=
⎡
⎢⎣¹³
−
0.46
n
⋅
(20
+
Rpri)_{⎥⎦⎤}
⋅
n
−
0.76
=
13
⋅
n
-
9.2
-
0.46
⋅
Rpri
-
0.76
>
1.1
→
13
⋅
n
-
0.46
⋅
Rpri
>
11.6
Selecting an Rpri (R7) equal to 47 Ω, the minimum transfer ratio should be equal to 2.55.
n = 5.6 has been selected.
The PWM_det pin network is composed of 3x220 kΩ resistors (R11 to R13) together with a
47 pF speed-up capacitor (C11). The value of the speed-up capacitor also avoids a
misdetection of the hard switching.
During normal operation the IC absorbs the following currents from the Vcc:
1. Effective base currents of the BJTs divided by n (5.6). A 39 mA_(MAX) is estimated.
2. Magnetizing current = 10 mA_(MAX)
3. L6520 power consumption: 8 mA_(MAX)
A maximum current of 57 mA_rms must be foreseen. For this reason, the IC power supply has
been connected in series with the resonant network (D4 and D5). This connection does not
interfere with the optimum preheating of the lamp’s cathodes, but introduces a little offset
(7.5 V typ.) into the lamp voltage.
This offset affects the EOL detection, but a different choice of values of the Zener diodes
(D6 and D7) makes the detection symmetrical. The two values, together with the resistance
values (R14 and R15), can be calculated through the following system of equations
(V_Lamp,MAX = 30 V and V_Lamp,min = -16 V):
Equation 7
⎨⎧^VLamp,MAX
⎩ ^VLamp,min
=
=
V_EOL
V_EOL
+ V_Z,D7
− V_Z,D6
+ I_BIAS
− I_BIAS
⋅ (R14 + R15)
⋅ (R14 + R15)
+ V_F,D6
− V_F,D7
Finally, a 4.7 µF is used as the Vcc bulk capacitor (C4) and two 100 nF ceramic capacitors
(C5) are placed close to the Vcc pins of the two ICs.
By allowing the startup network (R2 to R4) to pass through the upper cathode of the lamp,
the automatic re-lamp feature is easily obtained.
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Doc ID 018537 Rev 2