AN4104 Datasheet, PDF (6/13 Pages) STMicroelectronics – Using the STM32F0xx DMA controller

DMA controller description
AN4104
By default, the channel allocation and hardware priority (from 1 to 5 for STM32F0xx devices)
are set in order to assign the fastest peripherals to the highest priority channels. However,
this may not be true for some applications. In this case, the user can configure a software
priority for each channel (4 levels – from Very High to Low), which takes precedence over
the hardware priority.
1.3
DMA Interrupt management
An interrupt can be produced on a Half-transfer, Transfer complete or Transfer error for each
DMA channel. Separate interrupt enable bits are available for flexibility.
Table 2. DMA Interrupt requests
Interrupt events
Event Flags
Half Transfer
HTIF
Transfer Complete
Transfer Error
TCIF
TEIF
Control bit enable
HTIF
TCIF
TEIF
When a DMA transfer error occurs during a DMA read or a write access, the faulty channel
is automatically disabled through a hardware clear of its enable bit in the corresponding
Channel configuration register (DMA_CCRx). The channel's transfer error interrupt flag
(TEIF) in the DMA_IFR register is set and an interrupt is generated if the transfer error
interrupt enable bit (TEIE) in the DMA_CCRx register is set.
6/13
Doc ID 023131 Rev 1