PM0020 Datasheet, PDF (59/87 Pages) Solid States Devices, Inc – ULTRA FAST SWITCHING DEVICE

PM00020
12 ISC logic description
ISC logic description
12.1 Preliminary concepts
Memory organisation. The STR91xFA internal Flash consists of two banks: Main Flash
memory (Bank 0) and Secondary Flash memory (Bank 1).
Five dedicated sectors containing: MFG code, ID code, User code, Configuration
information, OTP, Security Bit. The dedicated sectors are physically placed in the Secondary
Flash, but are independent from it.
Sector write protection. Each sector in the Main and Secondary Flash has its own NVM
protection bit. All these protection bits reside in the Protection Sector. The content of this
sector is loaded in the ISC CONFIGURATION register at power-up and can be shifted out
with the ISC_CONFIGURATION instruction. If this bit is not set, the sector is unprotected, it
can be run time protected/unprotected by an MCU instruction (level 1 protection). When the
bit is set the sector is always protected (level 2 protection).
Using ISC instructions, you can program and erase the Protection Sector (see Configuration
Program Flow and ISC_ERASE instruction flow); after a modification of the Protection
Sector, the content of the ISC CONFIGURATION register is updated with the new value.
With ISC instructions you can modify all the sectors in the matrix regardless of the sector
protection status.
Readout protection. You can protect the Main and Secondary Flash content (codes) from
readout through the JTAG port by setting the Security bit. Once set, the Flash content
cannot be read, programmed or erased by JTAG. Only a full chip erase can erase the
Security bit.
During the start-up procedure the device is secured.
If an ISC_PROGRAM_SECURITY instruction is executed, the security status will be not
activated until the device exits from ISC mode, and, moreover, if the security bit is set and a
full chip erase is executed, also the new unsecured status will be not activated until the
device exits from ISC mode.
The non volatile security information is loaded in the SECURITY_BIT register at power-up
and is stored both in the Instruction register and the Default register. The security status can
be read by reading these registers.
OTP Sector. The OTP sector consists of 256 bits (8 words). It can be programmed through
the JTAG - or through ARM CPU- it can not be erased. Other unprogrammed words can
still be written at a later time. The OTP sector has a Lock bit which may be set by user
through JTAG. After the bit is set, the OTP is protected from further writing. Reading and
writing of the OTP Sector and programming the LOCK OTP BIT through JTAG are blocked if
the device is secured. The Lock bit value is loaded in the LOCK_OTP register and the
CONFIGURATION register at power-up. It can be shifted out with the configuration
information (see the LOCK_OTP and CONFIGURATION register, the
ISC_CONFIGURATION instruction flow and the Security ID and Lock OTP bit program
flows).
59/87