M24SR64-Y Datasheet, PDF (59/90 Pages) STMicroelectronics – Support of NDEF data structure

M24SR64-Y
I2C device operation
7.5
I²C timeout on clock period
During a data transfer on the I²C bus, if the serial clock high pulse or serial clock low pulse
exceeds t_{CL_RESET} value that is the maximum value specified in Table 78, the I²C logic
block is reset and any further incoming data transfer is ignored until the next valid Start
condition.
If the
pulse
serial clock high pulse
is under the maximum
is under
value of
the maximum value of
t_CLCH in Table 78, the
I^t2CC^HCl^Logaincdbtlhoecksiesrinaol tcrloecsketl.ow
For proper operation, the serial clock high pulse should not be higher than t_CHCL and lesser
than t_{CL_RESET}, and the serial clock low pulse should not be higher than t_CHCH and lesser
t_{CL_RESET}.
7.6
Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether a bus master or a slave device, releases the serial data (SDA) after sending eight
bits of data. During the 9th clock pulse period, the receiver pulls the SDA low to
acknowledge the receipt of the eight data bits.
7.7
Data input
During data input, the device samples serial data (SDA) on the rising edge of the serial clock
(SCL). For a correct device operation, the SDA must be stable during the rising edge of the
SCL, and the SDA signal must change only when the SCL is driven low.
7.8
I²C device address
The device address is the concatenation of the group number coded on 4 bits and the I²C
address coded on 3 bits, as shown in Table 68.
Table 68. I²C device address format
b7-b4
b3
b2
b1
b0
0b1010
1
1
0
0bx
Group number
E2 bit
E1 bit
E0 bit
0 = Request
1 = Answer
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