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STM32F405ZGT6 Datasheet, PDF (56/167 Pages) STMicroelectronics – ARM Cortex-M4 32b MCU+FPU, 210DMIPS, up to 1MB Flash/192+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera
Table 7. Alternate function mapping
Port
PA0
PA1
AF0
SYS
AF1
TIM1/2
TIM2_CH1
TIM2_ETR
TIM2_CH2
AF2
TIM3/4/5
TIM 5_CH1
TIM5_CH2
AF3
AF4
TIM8/9/10/11 I2C1/2/3
TIM8_ETR
AF5
SPI1/SPI2/
I2S2/I2S2ext
AF6
SPI3/I2Sext/
I2S3
PA2
TIM2_CH3
TIM5_CH3
TIM9_CH1
PA3
TIM2_CH4
TIM5_CH4
TIM9_CH2
PA4
PA5
TIM2_CH1
TIM2_ETR
TIM8_CH1N
SPI1_NSS
SPI1_SCK
SPI3_NSS
I2S3_WS
PA6
TIM1_BKIN
TIM3_CH1
TIM8_BKIN
SPI1_MISO
PA7
TIM1_CH1N
TIM3_CH2
TIM8_CH1N
SPI1_MOSI
PA8
MCO1
TIM1_CH1
I2C3_SCL
PA9
TIM1_CH2
I2C3_SMBA
PA10
TIM1_CH3
PA11
TIM1_CH4
PA12
TIM1_ETR
PA13
JTMS-SWDIO
PA14
PA15
PB0
JTCK-SWCLK
JTDI
TIM 2_CH1
TIM 2_ETR
TIM1_CH2N
TIM3_CH3
TIM8_CH2N
SPI1_NSS
SPI3_NSS/
I2S3S_WS
PB1
TIM1_CH3N
TIM3_CH4
TIM8_CH3N
PB2
PB3
JTDO/
TRACESWO
TIM2_CH2
PB4
JTRST
PB5
PB6
TIM3_CH1
TIM3_CH2
TIM4_CH1
SPI1_SCK
SPI1_MISO
I2C1_SMBA SPI1_MOSI
I2C1_SCL
I2S2_WS
SPI3_SCK
I2S3_CK
SPI3_MISO
SPI3_MOSI
I2S3_SD
PB7
TIM4_CH2
I2C1_SDA
PB8
PB9
PB10
PB11
PB12
PB13
PB14
TIM2_CH3
TIM2_CH4
TIM1_BKIN
TIM1_CH1N
TIM1_CH2N
TIM4_CH3
TIM4_CH4
TIM10_CH1 I2C1_SCL
TIM11_CH1 I2C1_SDA
I2C2_SCL
I2C2_SDA
I2C2_SMBA
TIM8_CH2N
SPI2_NSS
I2S2_WS
SPI2_SCK
I2S2_CK
SPI2_NSS
I2S2_WS
SPI2_SCK
I2S2_CK
SPI2_MISO
I2S2ext_SD
AF7
USART1/2/3/
I2S3ext
USART2_CTS
USART2_RTS
USART2_TX
USART2_RX
USART2_CK
USART1_CK
USART1_TX
USART1_RX
USART1_CTS
USART1_RTS
I2S3ext_SD
USART1_TX
USART1_RX
USART3_TX
USART3_RX
USART3_CK
USART3_CTS
USART3_RTS
AF8
AF9
AF10
UART4/5/
USART6
CAN1/CAN2/
TIM12/13/14
OTG_FS/ OTG_HS
AF11
ETH
AF12
FSMC/SDIO/
OTG_FS
AF13
DCMI
AF014 AF15
UART4_TX
UART4_RX
ETH_MII_CRS
ETH_MII _RX_CLK
ETH_RMII _REF_CLK
ETH_MDIO
EVENTOUT
EVENTOUT
EVENTOUT
OTG_HS_ULPI_D0 ETH _MII_COL
EVENTOUT
OTG_HS_SOF DCMI_HSYNC
EVENTOUT
OTG_HS_ULPI_CK
EVENTOUT
TIM13_CH1
TIM14_CH1
OTG_FS_SOF
ETH_MII _RX_DV
ETH_RMII _CRS_DV
DCMI_PIXCK
EVENTOUT
EVENTOUT
EVENTOUT
DCMI_D0
EVENTOUT
OTG_FS_ID
DCMI_D1
EVENTOUT
CAN1_RX
CAN1_TX
OTG_FS_DM
OTG_FS_DP
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
OTG_HS_ULPI_D1 ETH _MII_RXD2
EVENTOUT
OTG_HS_ULPI_D2 ETH _MII_RXD3 OTG_HS_INTN
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
CAN2_RX OTG_HS_ULPI_D7 ETH _PPS_OUT
DCMI_D10
EVENTOUT
CAN2_TX
FSMC_NL
DCMI_D5
DCMI_VSYNC
EVENTOUT
EVENTOUT
CAN1_RX
ETH _MII_TXD3
SDIO_D4
DCMI_D6
EVENTOUT
CAN1_TX
SDIO_D5
DCMI_D7
EVENTOUT
OTG_HS_ULPI_D3 ETH_ MII_RX_ER
CAN2_RX
CAN2_TX
OTG_HS_ULPI_D4
OTG_HS_ULPI_D5
OTG_HS_ULPI_D6
ETH _MII_TX_EN
ETH _RMII_TX_EN
ETH _MII_TXD0
ETH _RMII_TXD0
ETH _MII_TXD1
ETH _RMII_TXD1
TIM12_CH1
OTG_HS_ID
OTG_HS_DM
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT