SPEAR320-2 Datasheet, PDF (56/73 Pages) STMicroelectronics – Embedded MPU with ARM926 core, optimized for factory automation and consumer applications

Timing requirements
Figure 12. Output address signal waveforms for NAND Flash
FSMC_CSx
FSMC_ADDR_LE
FSMC_WE
FSMC_Dx
t_ALE
t_WE
t_IO
Address
SPEAr320
Figure 13. In/out data address signal waveforms for NAND Flash
FSMC_CSx
FSMC_WE
FSMC_Dx (out)
FSMC_RE
FSMC_Dx (in)
t_WE
t_IO
t_RE
Data Out
t_READ
t_{RE -> IO} t_{NFIO -> FFs}
Note:
Table 36. Timing characteristics for NAND Flash
Parameter
Min
t_CLE
t_ALE
t_WE (programmable by the Tset
bits in the FSMC registers)
t_RE (programmable by the Tset
bits in the FSMC registers)
t_IO (programmable by the Thiz
bits in the FSMC registers)
t_READ (programmable by the
Twait bits in the FSMC registers)
-3.9
-4.2
(((Tset+1) * t_HCLK ) - 3 ns)
(((Tset+1) * t_HCLK ) - 3 ns)
(((Thiz +1) * t_HCLK) - 3 ns)
((Twait+1)* t_HCLK
Max
2.8
2.6
(((Tset+1) * t_HCLK) + 3 ns)
(((Tset+1) * t_HCLK) + 3 ns)
(((Thiz +1) * t_HCLK )+ 3 ns)
Values in Table 36 are referred to the common internal source clock which has a period of
t_HCLK = 6 ns.
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