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STM32L011X3 Datasheet, PDF (55/115 Pages) STMicroelectronics – Access line ultra-low-power 32-bit MCU ARM-based Cortex-M0+, up to 16KB Flash, 2KB SRAM, 512B EEPROM, ADC
Electrical characteristics
STM32L011x3/4
Table 24. Current consumption in Run mode, code with data processing running from RAM
Symbol
Parameter
Conditions
Range 3,
VCORE=1.2 V,
VOS[1:0]=11
fHSE = fHCLK up to 16
MHz, included
fHSE = fHCLK/2 above
16 MHz
(PLL ON)(2)
Range 2,
VCORE=1.5 ,V,
VOS[1:0]=10
IDD (Run
from
RAM)
Supply current in
Run mode, code
executed from
RAM, Flash
switched OFF
MSI clock
Range 1,
VCORE=1.8 V,
VOS[1:0]=01
Range 3,
VCORE=1.2 V,
VOS[1:0]=11
fHCLK
Typ Max(1) Unit
1 MHz 115 140
2 MHz 205 240 µA
4 MHz 385 420
4 MHz 0.48 0.55
8 MHz 0.935 1.1
16 MHz 1.8
8 MHz 1.1
2
mA
1.4
16 MHz 2.1
2.5
32 MHz 4.5
4.9
65 kHz 22
38
524 kHz 67
91
µA
4.2 MHz 415 450
HSI16 clock source
(16 MHz)
Range 2,
VCORE=1.5 V,
VOS[1:0]=10
Range 1,
VCORE=1.8 V,
VOS[1:0]=01
16 MHz 1.95 2.2
mA
32 MHz 4.7
5.2
1. Guaranteed by characterization results at 125 °C, not tested in production, unless otherwise specified.
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).
Table 25. Current consumption in Run mode vs code type,
code with data processing running from RAM(1)
Symbol
Parameter
Conditions
IDD (Run
from
RAM)
Supply current in
Run mode, code
executed from
RAM, Flash
switched OFF
fHSE = fHCLK up to 16
MHz, included,
f1H6SME =HzfH(CPLLKL/2OaNb)o(2v)e
Range 3,
VCORE=1.2 V,
VOS[1:0]=11
Range 1,
VCORE=1.8 V,
VOS[1:0]=01
Dhrystone
CoreMark
Fibonacci
while(1)
Dhrystone
CoreMark
Fibonacci
while(1)
fHCLK
4 MHz
32 MHz
1. Guaranteed by characterization results, not tested in production, unless otherwise specified.
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).
3. CoreMark code is unable to run from RAM since the RAM size is only 2 Kbytes.
Typ Unit
385
-(3)
µA
350
340
4.5
-(3)
mA
4.2
3
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