STM32F101R6T6 Datasheet, PDF (55/79 Pages) STMicroelectronics – Low-density access line, ARM-based 32-bit MCU with 16 or 32 KB Flash, 5 timers, ADC and 4 communication interfaces

STM32F101x4, STM32F101x6
Electrical characteristics
Output driving current
The GPIOs (general-purpose inputs/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20 mA (with a relaxed V_OL/V_OH).
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2:
● The sum of the currents sourced by all the I/Os on V_DD, plus the maximum Run
consumption of the MCU sourced on V_DD, cannot exceed the absolute maximum rating
I_VDD (see Table 6).
● The sum of the currents sunk by all the I/Os on V_SS plus the maximum Run
consumption of the MCU sunk on V_SS cannot exceed the absolute maximum rating
I_VSS (see Table 6).
Output voltage levels
Unless otherwise specified, the parameters given in Table 35 are derived from tests
performed under the ambient temperature and V_DD supply voltage conditions summarized
in Table 8. All I/Os are CMOS and TTL compliant.
Table 35. Output voltage characteristics
Symbol
Parameter
Conditions
Min Max Unit
V_OL(1)
Output Low level voltage for an I/O pin
when 8 pins are sunk at the same time
CMOS port⁽²⁾,,
0.4
I_IO = +8 mA,
V
V_OH(3)
Output High level voltage for an I/O pin _{2.7 V < VDD < 3.6 V}
when 8 pins are sourced at the same time
V_DD–0.4
V_OL(1)
Output low level voltage for an I/O pin
when 8 pins are sunk at the same time
TTL port⁽²⁾
I_IO = +8 mA
V_OH(3)
Output high level voltage for an I/O pin
when 8 pins are sourced at the same time
2.7 V < V_DD < 3.6 V
2.4
0.4
V
V_OL(1)
Output low level voltage for an I/O pin
when 8 pins are sunk at the same time
I_IO = +20 mA⁽⁴⁾
1.3
V
V_OH ⁽³⁾
Output high level voltage for an I/O pin
when 8 pins are sourced at the same time
2.7 V < V_DD < 3.6 V
V_DD–1.3
V_OL(1)
Output low level voltage for an I/O pin
when 8 pins are sunk at the same time
I_IO = +6 mA⁽⁴⁾
0.4
V
V_OH(3)
Output high level voltage for an I/O pin
when 8 pins are sourced at the same time
2 V < V_DD < 2.7 V
V_DD–0.4
1. The I_IO current sunk by the device must always respect the absolute maximum rating specified in Table 6
and the sum of I_IO (I/O ports and control pins) must not exceed I_VSS.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. The I_IO current sourced by the device must always respect the absolute maximum rating specified in
Table 6 and the sum of I_IO (I/O ports and control pins) must not exceed I_VDD.
4. Based on characterization data, not tested in production.
Doc ID 15058 Rev 5
55/79