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STW4810_07 Datasheet, PDF (54/78 Pages) STMicroelectronics – Power management for multimedia processors
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Electrical and timing characteristics
5.3.5
LDO regulators
VPLL
Table 40. LDO regulators - VPLL
Symbol
Description
Test conditions
Min.
Typ.
VPLL regulator in normal mode / otherwise specified, VPLL = 1.8 V
VBAT
Input power supply Battery voltage
2.7
VPLL_SEL[1:0]
11 (default)
VOUT
Output voltage
10
-3%
01
00
IOUT
Output current
ISHORT
Short-circuit
limitation
95
IQ
Quiescent current IOUT = 0 mA
ILKG
Power-down
current
EN_VPLL = 0
Vpp = 0.3 V
PSRR(1)
Power supply
rejection
f < 10 kHz
10 kHz < f
<100 kHz
55
45
LIR
LDR
LIRT
LDRT
En(1)
Line regulation
Load regulation
Transient line
regulation
Transient load
regulation
Noise density
VBAT: [2.7; 4.8]V
IOUT: [0.1; 10] mA
ΔVBAT = 300 mV
tR = tF = 10 µs
IOUT = [0.1; 10] mA
tR = tF = 1 µs
at 1 KHz
BW = 100 Hz
3.6
1.8
1.3
1.2
1.05
3.5
130
30
1
1
1. Guaranteed by design
STw4810
Max.
Units
4.8
V
+3%
V
10
mA
165
mA
40
µA
1
µA
dB
dB
5
mV
10
mV
mV
mV
250
n---V---r--m---s-
Hz
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