STM32F105XX_11 Datasheet, PDF (51/103 Pages) STMicroelectronics – Connectivity line, ARM-based 32-bit MCU with 64/256 KB Flash, USB OTG, Ethernet

STM32F105xx, STM32F107xx
Electrical characteristics
5.3.8
All timings are derived from tests performed under ambient temperature and V_DD supply
voltage conditions summarized in Table 9.
Table 26. Low-power mode wakeup timings
Symbol
Parameter
Typ
Unit
t_WUSLEEP(1)
Wakeup from Sleep mode
1.8
µs
Wakeup from Stop mode (regulator in run mode)
3.6
t_WUSTOP(1)
Wakeup from Stop mode (regulator in low power mode)
5.4
µs
t_WUSTDBY(1)
Wakeup from Standby mode
50
µs
1. The wakeup times are measured from the wakeup event to the point in which the user application code
reads the first instruction.
PLL, PLL2 and PLL3 characteristics
The parameters given in Table 27 and Table 28 are derived from tests performed under
temperature and V_DD supply voltage conditions summarized in Table 9.
Table 27. PLL characteristics
Symbol
Parameter
Min⁽¹⁾
Max⁽¹⁾
Unit
f_{PLL_IN}
PLL input clock⁽²⁾
Pulse width at high level
3
12
MHz
30
ns
f_{PLL_OUT}
f_{VCO_OUT}
t_LOCK
Jitter
PLL multiplier output clock
PLL VCO output
PLL lock time
Cycle-to-cycle jitter
18
72
MHz
36
144
MHz
350
µs
300
ps
1. Based on characterization, not tested in production.
2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by f_{PLL_OUT}.
Table 28. PLL2 and PLL3 characteristics
Symbol
Parameter
Min⁽¹⁾
Max⁽¹⁾
Unit
f_{PLL_IN}
PLL input clock⁽²⁾
Pulse width at high level
3
5
MHz
30
ns
f_{PLL_OUT}
f_{VCO_OUT}
t_LOCK
Jitter
PLL multiplier output clock
PLL VCO output
PLL lock time
Cycle-to-cycle jitter
40
74
MHz
80
148
MHz
350
µs
400
ps
1. Based on characterization, not tested in production.
2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by f_{PLL_OUT}.
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