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MK50H28 Datasheet, PDF (51/64 Pages) STMicroelectronics – MULTI LOGICAL LINK FRAME RELAY CONTROLLER
MK50H28
AC TIMING SPECIFICATIONS CONTINUED
TA = 0 °C to 70 °C, VCC = +5 V ±5 percent, unless otherwise specified.
No Signal
13 RCLK
14 RCLK
15 RCLK
16 RCLK
17 RCLK
18 RD
19 RD
20 RD
21 RD
Symbol
TRCT
TRCH
TRCL
TRCR
TRCF
TRDR
TRDF
TRDH
TRDS
22 ALE/DAS TDOFF
23 ALE/DAS TDON
24 HLDA
THHA
25 HLDA
26 HLDA
T HLAH
THLAS
27 A
28 A
29 DAL
30 DAL
31 DAL
32 DAL
33 DAL
34 DAL
35 DAL
36 DAL
37 DAL
38 DAL
39 DAL
40 ALE
41 ALE
TXAS
TXAH
TAS
TAH
TRDAS
TRDAH
TWAH
TWDS
TWDH
TSRDS
TSRDH
TSWDH
TSWDS
TALES
TALHB
42 ALE
TALHS
43 DAS
TDASS
44 DAS
TDASH
45 DALI/DALO
BM)/BM1
46 DALI
47 DALI
48 DALI
TBMDE
TRIS
TRIH
TBMDD
Parameter
RCLK period
RCLK high time
RCLK low time
Rise time of RCLK
Fall time of RCLK
RD data rise time
RD data fall time
RD hold time after rising edge of RCLK
RD setup time prior to rising edge of
RCLK
Bus Master driver disable
Bus Master driver enable after rising
edge T1 SYSCLK
Delay to falling edge of HLDA from
falling edge of HOLD (Bus Master)
HLDA input setup time
Delay to rising edge HLDA from rising
edge HOLD
Address setup time
Address hold time
Address setup time
Address hold time
Data setup time (Bus Master read)
Data hold time (Bus Master read)
Address hold time (Bus Master write)
Data setup time (Bus Master write)
Data hold time (Bus Master write)
Data setup time (Bus Slave read)
Data hold time (Bus slave read)
Data hold time (Bus slave write)
Data setup time (Bus slave write)
ALE setup time
ALE hold time (asserted to de-
asserted) (DMA Burst)
ALE hold time (asserted to 3-State)
(Single DMA cycle)
DAS setup time from falling edge of T2
SYSCLK (Bus Master)
DAS hold time from rising edge of
SYSCLK (Bus Master)
Bus Master driver enable (from 3-
State to driven) (Bus Master)
DALI setup time (Bus Master read)
DALI hold time (Bus Master read)
Bus Master driver disable (from driven
to 3-State) (Bus Master)
Notes
Output Delay
Output Delay
Output Delay
Output Delay
Output Delay
Output Delay
Output Delay
Output Delay
Output Delay
Output Delay
Output Delay
Output Delay
Output Delay
Output Delay
Output Delay
Output Delay
Output Delay
Output Delay
Min.
20
8
8
0
0
0
0
2
8
0
0
0
10
10
0
15
10
10
10
5
Typ.
Max.
8
8
8
8
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
ns
20
ns
ns
ns
ns
30
ns
20
ns
35
ns
20
ns
ns
ns
15
ns
25
ns
25
ns
25
ns
25
ns
ns
ns
30
ns
15
ns
20
ns
25
ns
15
ns
25
ns
15
ns
25
ns
20
ns
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