ST7LITEUSX Datasheet, PDF (50/108 Pages) STMicroelectronics – 8-bit MCU with single voltage Flash memory, ADC, timers

ST7LITEUSx
LITE TIMER (Cont’d)
10.1.6 Register Description
LITE TIMER CONTROL/STATUS REGISTER
(LTCSR)
Read / Write
Reset Value: 0000 0x00 (0xh)
7
0
ICIE ICF
TB
TBIE
TBF
WDG
R
WDGE
WDG
D
Bit 7 = ICIE Interrupt Enable.
This bit is set and cleared by software.
0: Input Capture (IC) interrupt disabled
1: Input Capture (IC) interrupt enabled
Bit 6 = ICF Input Capture Flag.
This bit is set by hardware and cleared by software
by reading the LTICR register. Writing to this bit
does not change the bit value.
0: No input capture
1: An input capture has occurred
Note: After an MCU reset, software must initialise
the ICF bit by reading the LTICR register
Bit 5 = TB Timebase period selection.
This bit is set and cleared by software.
0: Timebase period = t_OSC * 8000 (1ms @ 8 MHz)
1: Timebase period = t_OSC * 16000 (2ms @ 8
MHz)
Bit 4 = TBIE Timebase Interrupt enable.
This bit is set and cleared by software.
0: Timebase (TB) interrupt disabled
1: Timebase (TB) interrupt enabled
Bit 3 = TBF Timebase Interrupt Flag.
This bit is set by hardware and cleared by software
reading the LTCSR register. Writing to this bit has
no effect.
0: No counter overflow
1: A counter overflow has occurred
Bit 2 = WDGRF Force Reset/ Reset Status Flag
This bit is used in two ways: it is set by software to
force a watchdog reset. It is set by hardware when
a watchdog reset occurs and cleared by hardware
or by software. It is cleared by hardware only when
an LVD reset occurs. It can be cleared by software
after a read access to the LTCSR register.
0: No watchdog reset occurred.
1: Force a watchdog reset (write), or, a watchdog
reset occurred (read).
Bit 1 = WDGE Watchdog Enable
This bit is set and cleared by software.
0: Watchdog disabled
1: Watchdog enabled
Bit 0 = WDGD Watchdog Reset Delay
This bit is set by software. It is cleared by hard-
ware at the end of each t_WDG period.
0: Watchdog reset not delayed
1: Watchdog reset delayed
LITE TIMER INPUT CAPTURE
(LTICR)
Read only
Reset Value: 0000 0000 (00h)
REGISTER
7
0
ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0
Bits 7:0 = ICR[7:0] Input Capture Value
These bits are read by software and cleared by
hardware after a reset. If the ICF bit in the LTCSR
is cleared, the value of the 8-bit up-counter will be
captured when a rising or falling edge occurs on
the LTIC pin.
Table 16. Lite Timer Register Map and Reset Values
Address (Hex.) Register Label
0B
LTCSR
Reset Value
0C
LTICR
Reset Value
7
ICIE
0
ICR7
0
6
ICF
0
ICR6
0
5
TB
0
ICR5
0
4
TBIE
0
ICR4
0
3
TBF
0
ICR3
0
2
1
WDGRF WDGE
x
0
ICR2
0
ICR1
0
0
WDGD
0
ICR0
0
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