ST62T85B Datasheet, PDF (50/76 Pages) STMicroelectronics – 8-BIT OTP/EPROM MCU WITH LCD DRIVER, EEPROM AND A/D CONVERTER

ST62T85B/E85B
REGISTERS (Cont’d)
UART Control Register (UARTCR)
Address: D7h, Read/Write
7
0
RXRDY TXMT RXIEN TXIE N BR2 BR1 BR0 DAT9
Bit 7 = RXRDY. Receiver Ready. This flag be-
comes active as soon as a complete byte has
been received and copied into the receive buffer. It
may be cleared by writing a zero to it. Writing a
one is possible. If the interrupt enable bit RXIEN is
set to one, a software interrupt will be generated.
Bit 6 = TXMT. Transmitter Empty. This flag be-
comes active as soon as a complete byte has
been sent. It may be cleared by writing a zero to it.
It is automatically cleared by the action of writing a
data value into the UART data register.
Bit 5 = RXIEN. Receive Interrupt Enable. When
this bit is set to 1, the receive interrupt is enabled.
Writing to RXIEN does not affect the status of the
interrupt flag RXRDY.
Bit 4 = TXIEN. Transmit Interrupt Enable. When
this bit is set to 1, the transmit interrupt is enabled.
Writing to TXIEN does not affect the status of the
interrupt flag TXRDY.
Bit 3-1= BR2..BR0. Baudrate select. These bits
select the operating baud rate of the UART, de-
pending on the frequency of fOSC. Care should be
taken not to change these bits during communica-
tion as writing to these bits has an immediate ef-
fect.
Bit 0 = DAT9. Parity/Data Bit 9. This bit represents
the 9th bit of the data character that is received or
transmitted. A write to this bit sets the level for the
bit 9 to be transmitted, so it must always be set to
the correct level before transmission. If used as
parity, the value has first to be calculated by soft-
ware. Reading this bit will return the 9th bit of the
received character.
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