AN2738 Datasheet, PDF (50/54 Pages) STMicroelectronics – L6390 half-bridge gate driver

Layout suggestions
12 Layout suggestions
AN2738
Typically, for power applications using high voltages and large load currents, the board
layout of all circuits related to the power stage is important. Board layout includes several
aspects, such as track dimensions (length and width), circuit areas, but also the proper
routing of the traces and the optimized reciprocal arrangement of the various system
elements and power sources in the PCB area.
Reasons to give particular attention to the PCB layout include EMI issues (both induced and
perceived by the application) and over-voltage spikes due to parasitic inductances along the
PCB traces, the proper connection of the sense blocks, the logic inputs and the analog
outputs of the L6390 device. In fact, the L6390 IC not only has the function of driving the
power stage, but also embeds analog sensing blocks such as comparator and op-amps. For
example, especially regarding multi-phase power stages, it is important to keep the current
reading, performed through the integrated op-amp, from ground noise.
In Figure 45 some layout guidelines and suggestions for a 3-phase application are provided.
Figure 45. Layout suggestion for a 3-phase power system
MINIMIZE
THIS AREA
MINIMIZE THE LENGHT
OF THESE PATHS
TRACKS SWITCHING WITH HIGH VOLTAGE
TRANSITIONS SHOULD BE KEPT FAR FROM
THE LOGIC AND OPAMP ANALOG LINES
H.V.
L6390
L6390
L6390
HVG
inputs
control signals
OUT
LIN
HIN
LVG
to phase 1
LP1
uC
+
ADC
GND
OPOUT
GND
LP2
USE RSENSE
WITH LOW
PARASITIC
INDUCTANCE
LP3
DRIVER GROUND
MINIMIZE
TO LIMIT
THE BELOW
GROUND SPIKE
ON OUT PIN
LP4
to phase 2
LP1
LP2
to phase 3
LP1
+
BULK
CAPACITOR
LP2
LP3
LP3
LP4
LP4
SIGNAL GROUND
MINIMIZE TO LIMIT THE NOISE
ON THE INPUT LOGIC SIGNALS AND ON THE
ANALOG OPAMP OUTPUT
POWER GROUND
LP5
NOT CRITICAL
As explained in Section 8.9, the gate driving PCB traces should be designed to be as short
as possible and the area of the circuits should be minimized to avoid the sensitivity of such
structures to the surrounding noise. Typically, a good power system layout keeps the power
IGBTs (or MOSFETs) of each half-bridge as close as possible to the related gate driver.
In Figure 45 a set of parasitic inductances related to the different circuit tracks is shown. The
various groups of inductances may have undesired effects which should be limited as much
as possible. Moreover, note that Figure 45 emphasizes parasitic inductances located on the
lines usually managing high voltages and fast current transitions, which are very noisy.
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Doc ID 14589 Rev 2