USBDFXXW5 Datasheet, PDF (5/9 Pages) STMicroelectronics – EMI FILTER AND LINE TERMINATION FOR USB DOWNSTREAM PORTS

Fig. A4: USBDFxxW5 ESD clamping behavior
USBDFxxW5
V_PP
ESD Surge
Rg
S1
R
S2
Rd
Vinput
Rd
V_BR
Voutput
V_BR
USBDFxxW5
Rload
Device
to be
protected
To have a good approximation of the remaining voltages at both Vin and Vout stages, we give the typical
dynamical resistance value Rd. By taking into account these following hypothesis : Rt>Rd, Rg>Rd and
Rload>Rd, it gives these formulas:
Vinput = ^{Rg.VBR + Rd.Vg}
Rg
Voutput = ^{Rt.VBR + Rd.Vinput}
Rt
The results of the calculation done for V_PP=8kV, Rg=330Ω (IEC61000-4-2 standard), V_BR=7V (typ.)
and Rd = 1Ω (typ.) give:
Vinput = 31.2 V
Voutput = 7.95 V
This confirms the very low remaining voltage across the device to be protected. It is also important to note
that in this approximation the parasitic inductance effect was not taken into account. This could be few
tenths of volts during few ns at the Vin side. This parasitic effect is not present at the Vout side due the low
current involved after the resistance R.
The measurements done here after show very clearly (Fig. A6) the high efficiency of the ESD protection :
- no influence of the parasitic inductances on Vout stage
- output clamping voltage very close to V_BR (positive strike) and -V_F (negative strike)
Fig. A5: Measurement board
ESD
SURGE
16kV
Air
Discharge
TEST BOARD
Vin
Vout
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