TDA7535_06 Datasheet, PDF (5/9 Pages) STMicroelectronics – DELTA/SIGMA CASCADE 20 BIT STEREO DAC

Figure 2. I²S Timings
SDATA
FSYNC
SCK
Valid
t_sckr
Valid
t_sckf
t_lrw- t_lrw+
t_sds
t_sckpl
t_sdh
t_sckph
t_sck
TDA7535
Timing
Description
Minimum
t_sck
Clock Cycle⁽¹⁾
1/(64*Fs) -
150ps_RMS
t_sckpl
SCK Phase Low
0.5*t_sck - 1%
t_sckph
SCK Phase High
0.5*t_sck - 1%
t_lrw-
FSYNC switching time window before SCK falling edge⁽²⁾
0
t_lrw+
FSYNC switching time window after SCK falling edge⁽²⁾
0
t_sds
SDATA setup time
60
t_sdh
SDATA hold time
30
t_sckr
SCK rise time
t_sckf
SCK fall time
(1)
(2)
SCK clock defines the Fs, being
FSYNC switches inside the time
the Sample Rate. This input clock needs
window as specified w.r.t. to falling edge
a jitter below
of SCK
~212ps_RMS
Figure 3. Power Up & Reset Sequence
Maximum
1/(64*Fs) +
150ps_RMS
0.5*t_sck +1%
0.5*t_sck +1%
0.125*t_sck-10
0.125*t_sck-10
22
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
V_DD
RESET
T_RES
T_RES
Min 50ms
D02AU1418
5/9