TDA7521 Datasheet, PDF (5/11 Pages) STMicroelectronics – Analog Front End

Figure 2. TDA7521 timings in 768×Fs mode
TDA7521
(1
(2
(3.A)
(3.B)
(3.C)
(3.D)
AC
BD
E
F
AC
BD
E
F (4
BD
E
F
AC
BD
E
F
(5
RF
RF
RF
RF
RF
RF
RF
RF
(6
RF
RF
RF
RF
RF
RF
RF
RF
(7
RBR
ER
FR A R B R
ER
FR
(8
ARBR
ER
FR A R B
R
ER
F R ₍₉
(10)
(11)
(12.A)
(12.B)
(12.C)
Fig.3.
A349 timing: (1) External clock ( 768 × F_S mode); (2) Servo clock (servo data change on its
rising edge, while RF data change on the falling edge); (3.A, 3.B, 3.C, 3.D) Internally generated
96 × F_S clocks for Servo ADC; (4) Servo data IN; (5) Servo data OUT; (6) RF data IN; (7) RF
data OUT; (8) AC/RF/BD/RF/E/RF/F/RF data stream before digital MUX; (9) Output
AC/RF/BD/RF/E/RF/F/RF; (10) Synthesized clock; (11) Generic Bitstream Input; (12.A, 12.B,
12.C) Possible synthesized 256 × F_S (depending on the initial conditions)
5/11