M40SZ100Y Datasheet, PDF (5/19 Pages) STMicroelectronics – 5V or 3V NVRAM SUPERVISOR FOR LPSRAM

Figure 7. Hardware Hookup
Unregulated
Voltage
3.0V, 3.3V or 5V
Regulator
VIN VCC
VCC
VOUT
0.1µF
From Microprocessor
R1
R2
M40SZ100Y
M40SZ100W
E
RSTIN ECON
PFI
PFO
VSS
VBAT⁽¹⁾
RST
BL
M40SZ100Y, M40SZ100W
0.1µF
VCC
1Mb or 4Mb
LPSRAM
E
To Microprocessor NMI
To Microprocessor Reset
To Battery Monitor Circuit
Note: 1. User supplied for the 16-pin package
AI04767
MAXIMUM RATING
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rat-
ing conditions for extended periods may affect de-
vice reliability. Refer also to the
STMicroelectronics SURE Program and other rel-
evant quality documents.
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
T_STG
Storage Temperature (V_CC Off)
SNAPHAT
–40 to 85
°C
SOIC
–55 to 125
°C
T_SLD(1)
Lead Solder Temperature for 10 seconds
260
°C
V_IO
Input or Output Voltages
–0.3 to V_CC +0.3
V
V_CC
Supply Voltage
M40SZ100Y
–0.3 to 7
V
M40SZ100W
–0.3 to 4.6
V
I_O
Output Current
P_D
Power Dissipation
20
mA
1
W
Note: 1. Reflow at peak temperature of 215°C to 225°C for < 60 seconds (total thermal budget not to exceed 180°C for between 90 to 120
seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
5/19