AN3270 Datasheet, PDF (5/23 Pages) STMicroelectronics – Using the STM8L16x AES hardware accelerator

AN3270
AES hardware accelerator operation modes
Figure 3. AES algorithm in encryption mode
Enable AES clock⁽¹⁾
Configure AES peripheral:
Select encryption mode⁽²⁾
Enable computation complete
interrupt⁽³⁾
Enable AES to start processing
Counter = 0
Input phase
Write encryption key EK[counter]
in DINR register
Write plain text PT[counter]
in DINR register
Counter++
Counter = 16?⁽⁴⁾
Computation phase
Is computation complete?
Counter = 0
Output phase
Read cypher text CT[counter]
from DOUTR register
Counter++
Counter = 16?⁽⁴⁾
End
MS19717V1
1. The AES peripheral clock must be enabled to allow write access to the AES registers.
2. Mode configuration must be done before enabling the AES.
3. If required, the Computation Complete interrupt can be enabled using the Computation Complete Interrupt
Enable (CCIE) bit.
4. The AES hardware accelerator requires the 16 bytes of data (128 bits) to be written/read from MSB (16th
data byte) to LSB (1st data byte) that is why the Counter is initialized to 0.
Doc ID 17919 Rev 2
5/23