AN1879 Datasheet, PDF (5/8 Pages) STMicroelectronics – How to use the M41ST87W tamper detect and RAM clear

AN1879
Description
1.4
RAM clear data
Depending on the process technology used to manufacture the external SRAM, clearing
the memory may require varying durations of negative potential on the VCC pin. The
M41ST87W device allows the user to program the time needed for their particular
application. The control bits CLRPW0 and CLRPW1, located in the day register, determine
the duration of the tCLR pulse width during a tamper event (see Figure 2: "Tamper output
timing" ). Thus, users can control the voltage and duration of the negative pulse enabling
them to configure the circuit for many different LPSRAMs.
Figure 2: Tamper output timing
TP
CLR
t_CLRD
t _CLR
RST
t _rec
VOUT
High-Z
IRQ/OUT
ECON
Tamper
Event
(TB Bit set)
High-Z
Note: see M41ST87W datasheet for timing details.
1.5
Tamper timestamp
When the device is tampered with, and regardless of which tamper occurs first, a time
stamp freezing the update of the clock registers will occur to let the user know when it was
tampered with. The tamper bits (TB1 or TB2 in the flag register) will be set immediately.
Therefore, when tampering occurs, the user may elect to first read the time registers to
determine exactly when the tamper event occurred, then read the flag register to see which
tamper condition was triggered. The clock will update to the current time after resetting the
TEB bit in the tamper registers. The appropriate TEB bit must always be reset to '0' in order
to read the current time. The tamper detect function operates in V_CC as well as in battery
backup.
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