STTS2004 Datasheet, PDF (47/58 Pages) STMicroelectronics – 16 bytes Page Write within 5 ms

STTS2004
DC and AC parameters
Table 33. AC characteristics of STTS2004 for SMBus and I²C compatibility timings
Symbol
Parameter
Min Max Units
f_SCL
I²C clock frequency
10 1000 kHz
t_HIGH
t_LOW(1)
t_R(2)
t_F(2)
Clock high period
Clock low period
Clock/data rise time
Clock/data fall time
260 –
ns
500 –
ns
– 120 ns
– 120 ns
t_SU:DAT
Data-in setup time
50
–
ns
t_HD:DI
Data-in hold time
0
–
ns
t_HD:DAT
t_SU:STA(3)
Data-out hold time
Repeated start condition setup time
0 350 ns
260 –
ns
t_HD:STA
Hold time after (repeated) start condition. After this period,
the first clock cycle is generated.
260
–
ns
t_SU:STO Stop condition setup time
260 –
ns
t_BUF
t_W(4)
t_timeout(5)
Bus free time between stop (P) and start (S) conditions
WRITE time for EEPROM
Bus timeout
500 –
ns
–
5
ms
25 35 ms
t_POFF
Warm power cycle off time
1
–
ms
t_INIT
C_B(6)
Time from power-on to first command
Capacitive load for each bus line
10
–
ms
550 pf
1. The STTS2004 will not initiate clock stretching which is an I²C bus optional feature.
2. Guaranteed by design and characterization, not necessarily tested.
3. For a restart condition, or following a WRITE cycle.
4. This parameter reflects maximum WRITE time for EEPROM.
5. The I²C bus masters can terminate a transaction in process and reset devices on the bus by asserting SCL
low for t_TIMEOUT,MAX or longer. The STTS2004, upon detecting this condition, will reset communication and
be able to receive a new START condition no later than t_TIMEOUT,MAX. The STTS2004 will not reset if SCL
stretching is less than t_TIMEOUT,MIN.
6. The maximum bus capacitance allowable may vary from this value depending on the actual operating
voltage and frequency of the application.
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