TDA7572 Datasheet, PDF (45/64 Pages) STMicroelectronics – 200W mono bridge PWM amplifier with built-in step-up converter

TDA7572
DAC
In case of Fratio = "11" the configuration is still for full band. The input sample rate for this
case is 192kHz (Fs) and the first x4 interpolator has to be implemented off-line in the DSP.
For the first x2 interpolator could be used the precedent, for the second one should be used
the following:
Oversampling
Increasing word rate from 2Fs to 4Fs.
Filter Type
Remez filter, half band
Taps, bit 7, 12
Attenuation 50db attenuation out of 0.77*(2Fs)
Coefficients It is an Half-Band filter then we have only 3
coefficients (see following)
Coefficients: -190, 1199,2047,…
To implement the first interpolator are necessary 28 memory access, 14 sum and14 MAC
(multiply with accumulation) at rate Fs. For the second one are, instead, enough 4 memory
access, 2 sum and 2 MAC at rate 2Fs. In the following schematic is reported the structure
for the two interpolator eventually to implement in the DSP.
Figure 8.
Two interpolator structure diagram
18
bit
RAM
32x18bit
19
30
bit
bit
12
bit
18
bit
ROM
16x12bit
34
bit
REG
AC00020
The I²S format is used to transfer audio samples:
Figure 9. I²S format diagram
WS
LEFT
SCL
RIGHT
SDA
MSB
LSB
MSB
LSB
MSB
AC00021
Where the WS is a clock at frequency Fs(48,96,192kHz) and discern which channel is
transferred, where the SCL is the interface clock at 64*Fs(3.07, 6.14, 12.29MHz). The SDA
are the bit transferred, 32 for each channel. Only the first 18 bits are taken into account and
only one channel. The Control register bit L/R selects the channel amplified.
The internal clock used to clock the DAC logic is obtained from the PLL that lock to the I2S
clock present on pin SCL. In order to work the PLL needs a RC series network connected to
pin PLL/INLEVEL0 (pin 44). Optimal value are C=100nF, R=33Ohm with in parallel an 1.8pF
capacitance
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