STR91XF_07 Datasheet, PDF (44/73 Pages) STMicroelectronics – ARM966E-S TM 16/32-Bit Flash MCU with Ethernet, USB, CAN, AC motor control, 4 timers, ADC, RTC, DMA

Memory mapping
STR91xF
Notes for Figure 9: STR91xF memory map on page 45:
Notes: 1 Either of the two Flash memories may be placed at CPU boot address 0x0000.0000. By default,
the primary Flash memory is in boot position starting at CPU address 0x0000.0000 and the
secondary Flash memory may be placed at a higher address following the end of the primary
Flash memory. This default option may be changed using the STR91xx device configuration
software, placing the secondary Flash memory at CPU boot location 0x0000.0000, and then
the primary Flash memory may be placed at a higher address.
2 The local SRAM (64KB or 96KB) is aliased in three address windows. A) At 0x0400.0000 the
SRAM is accessible through the CPU’s D-TCM, at 0x4000.0000 the SRAM is accessible
through the CPU’s AHB in buffered accesses, and at 0x5000.0000 the SRAM is accessible
through the CPU’s AHB in non-buffered accesses. An AHB bus master other than the CPU can
access SRAM in all three aliased windows, but these accesses are always non-buffered. The
CPU is the only AHB master that can performed buffered writes.
3 APB peripherals reside in two AHB-to-APB peripheral bridge address windows, APB0 and
APB1. These peripherals are accessible with buffered AHB access if the CPU addresses them
in the address range of 0x4800.0000 to 0x4FFF.FFFF, and non-buffered access in the address
range of 0x5800.0000 to 0x5FFF.FFFF.
4 Individual peripherals on the APB are accessed at the listed address offset plus the base
address of the appropriate AHB-to-APB bridge.
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