ST10R167 Datasheet, PDF (44/63 Pages) STMicroelectronics – 16-BIT ROMLESS MCU

ST10R167
XX - ELECTRICAL CHARACTERISTICS (continued)
The real minimum value for TCL depends on the
jitter of the PLL. The PLL tunes F_CPU to keep it
locked on F_XTAL. The relative deviation of TCL is
the maximum when it is refered to one TCL
period. It decreases according to the formula and
to the Figure 12 given below. For N periods of
TCL the minimum value is computed using the
corresponding deviation D_N:
TCL _{M I N}
=
TCLNOM ×

^{1 –}

--₁-^D---₀--^N-₀----_{}
DN= ±(4 – N ⁄ 15)[%]
where N = number of consecutive TCL periods
and 1 ≤ N ≤ 40. So for a duration of 3 TCL periods
(N = 3):
D₃
= 4 - 3/15 = 3.8%
3TCL_min = 3TCL_NOM x (1 - 3.8/100)
= 3TCL_NOM x 0.962
3TCL_min = (57.72ns at f_CPU = 25MHz)
This is especially important for bus cycles using
wait states and for the operation of timers, serial
interfaces, etc. For all slower operations and
longer periods (e.g. pulse train generation or
measurement, lower Baud rates, etc.) the
deviation caused by the PLL jitter is negligible.
Figure 12 : Approximated maximum PLL jitter
Max.jitter [%]
±4
This approximated formula is valid for
1 ≤ N ≤ 40 and 10MHz ≤ f_CPU ≤ 25MHz.
±3
±2
±1
24
8
16
N
32
XX.4.7 - Memory cycle variables
The tables below use three variables which are derived from the BUSCONx registers and represent the
special characteristics of the programmed memory cycle. The following table describes how these
variables are to be computed.
Symbol
t_A
t_C
t_F
Description
ALE Extension
Memory Cycle Time wait states
Memory Tristate Time
Values
TCL * <ALECTL>
2TCL * (15 - <MCTC>)
2TCL * (1 - <MTTC>)
44/63