AN2744 Datasheet, PDF (44/56 Pages) STMicroelectronics – ST7538Q power line FSK transceiver

Board description
AN2744
The startup phase could also be critical for the SMPS as output overshoot occurs if the
circuit is not properly designed. Care must be taken in designing a proper clamp network in
order to prevent voltage spikes due to leakage inductance from exceeding the breakdown
voltage of the device (730 V minimum value).
The startup transient is shown in Figure 43. Note that the maximum drain-source voltage
doesn't exceed the minimum breakdown voltage BVDSS, with a reasonable safety margin.
Finally, load regulation is presented in Figure 42 and Figure 43 for different load conditions.
The voltage ranges from 10 V to 9.3 V, within the requested tolerance.
Figure 40. Typical waveforms at 230 V_AC: open Figure 41. Typical waveforms at 230 V_AC: full
load
load
V_DD
I_OUT
V_DD
V_DS
I_OUT
V_DS
Ch1 Freq - 9.62kHz; Ch2 Mean - 9.90V
Figure 42. Typical waveforms at 265 V_AC:
short-circuit
Ch1 Freq - 57.71kHz; Ch2 Mean - 13.79V; Ch4 Max -
503mA
Figure 43. Typical waveforms at 265 V_AC:
startup
V_DD
V_DS
I_OUT
V_DS
V_DD
I_OUT
Ch2 Freq - 23.50Hz; Ch4 Max - 2.08A; Ch4 Mean - 383mA
Ch1 Max - 702V; Ch2 Mean - 19.72V; Ch4 Max - 500mA
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