STA323W_08 Datasheet, PDF (43/77 Pages) STMicroelectronics – 2.1-channel high-efficiency digital audio system

STA323W
Register descriptions
7.3
Configuration register C (address 0x02)
7.3.1
7.3.2
D7
Reserved
0
D6
CSZ4
1
D5
CSZ3
0
D4
CSZ2
0
D3
CSZ1
0
D2
CSZ0
0
D1
OM1
1
D0
OM0
0
DDX^® power-output mode
Table 26. DDX^® power-output mode
Bit R/W RST
Name
Description
1:0 RW 10 OM[1:0]
Selects configuration of DDX^® output.
The DDX^® power output mode selects how the DDX^® output timing is configured. Different
power devices can use different output modes. The recommended use is OM = 10. When
OM = 11 the CSZ bits determine the size of the DDX^® compensating pulse.
Table 27. DDX^® output modes
OM[1,0]
Output stage - mode
00
Not used
01
Not used
10
Recommended
11
Variable compensation
DDX^® variable compensating pulse size
The DDX^® variable compensating pulse size is intended to adapt to different power stage
ICs. Contact ST for support when using this function.
Table 28. DDX^® compensating pulse
CSZ[4:0]
Compensating pulse size
00000
00001
…
10000
…
11111
0 clock period compensating pulse size
1 clock period compensating pulse size
…
16 clock period compensating pulse size
…
31 clock period compensating pulse size
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