VND7004AY Datasheet, PDF (4/47 Pages) STMicroelectronics – Double channel high-side driver with MultiSense analog feedback for automotive applications

List of figures
List of figures
VND7004AY
Figure 1: Block diagram ..............................................................................................................................5
Figure 2: Configuration diagram (top view).................................................................................................6
Figure 3: Current and voltage conventions.................................................................................................7
Figure 4: Switching time and Pulse skew .................................................................................................17
Figure 5: MultiSense timings (current sense mode) .................................................................................17
Figure 6: Multisense timings (chip temperature and VCC sense mode) ..................................................18
Figure 7: TDSTKON..................................................................................................................................18
Figure 8: Latch functionality - behavior in hard short circuit condition (TAMB << TTSD) ........................20
Figure 9: Latch functionality - behavior in hard short circuit condition......................................................20
Figure 10: Latch functionality - behavior in hard short circuit condition (autorestart mode + latch off) ....21
Figure 11: Standby mode activation .........................................................................................................21
Figure 12: Standby state diagram.............................................................................................................22
Figure 13: OFF-state output current .........................................................................................................22
Figure 14: Standby current .......................................................................................................................22
Figure 15: IGND(ON) vs. Iout ...................................................................................................................22
Figure 16: Logic Input high level voltage ..................................................................................................22
Figure 17: Logic Input low level voltage....................................................................................................23
Figure 18: High level logic input current ...................................................................................................23
Figure 19: Low level logic input current ....................................................................................................23
Figure 20: Logic Input hysteresis voltage .................................................................................................23
Figure 21: FaultRST Input clamp voltage .................................................................................................23
Figure 22: Undervoltage shutdown...........................................................................................................23
Figure 23: On-state resistance vs. Tcase .................................................................................................24
Figure 24: On-state resistance vs. VCC ...................................................................................................24
Figure 25: Turn-on voltage slope ..............................................................................................................24
Figure 26: Turn-off voltage slope ..............................................................................................................24
Figure 27: Won vs. Tcase .........................................................................................................................24
Figure 28: Woff vs. Tcase .........................................................................................................................24
Figure 29: OFF-state open-load voltage detection threshold ...................................................................25
Figure 30: Vsense clamp vs. Tcase..........................................................................................................25
Figure 31: Vsenseh vs. Tcase ..................................................................................................................25
Figure 32: Application diagram .................................................................................................................27
Figure 33: Simplified internal structure .....................................................................................................27
Figure 34: MultiSense and diagnostic – block diagram ............................................................................29
Figure 35: MultiSense block diagram .......................................................................................................30
Figure 36: Analogue HSD – open-load detection in off-state ...................................................................31
Figure 37: Open-load / short to VCC condition.........................................................................................32
Figure 38: GND voltage shift ....................................................................................................................33
Figure 39: PowerSSO-36 PC board .........................................................................................................34
Figure 40: Rthj-amb vs PCB copper area in open box free air conditions ...............................................35
Figure 41: PowerSSO-36 thermal impedance junction ambient single pulse ..........................................36
Figure 42: Thermal fitting model for PowerSSO-36..................................................................................36
Figure 43: Maximum turn off current versus inductance ..........................................................................38
Figure 44: PowerSSO-36 package outline ...............................................................................................39
Figure 45: PowerSSO-36 reel 13" ............................................................................................................41
Figure 46: PowerSSO-36 carrier tape ......................................................................................................42
Figure 47: PowerSSO-36 schematic drawing of leader and trailer tape ..................................................43
Figure 48: PowerSSO-36 marking information .........................................................................................43
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