TDA7331 Datasheet, PDF (4/7 Pages) STMicroelectronics – SINGLE CHIP RDS DEMODULATOR+ FILTER

TDA7331
Figure 1. RDS timing diagram
CLOCK
LINE
DATA
LINE
OUTPUT TIMING
The RDS (1187.5Hz) output clock on RDCL line
is synchronized to the incoming data.
According to the internal PLL lock condition data
change can result on the falling or on the rising
clock edge. (see Fig. 1)
Whichever clock edge is used by the decoder
(rising or falling edge) the data will remain valid
for 416.7 µsec after the clock transition.
OSCILLATOR CONTROLS (FSEL, OSEL)
Three different crystal frequencies can be used.
The adaption of the internal clock divider to the
external crystal is achieved via the input pin
FSEL. See the followings table for reference:
Crystal
4.332MHz
8.664MHz
17.328MHz
FSEL (pin configuration)
connected to GND or open
connected to Vs
external resistor of 100K to Vs
A special mode is introduced to reduce EMI. With
pin OSEL connected to GND the internal oscilla-
tor is switched off and an external sinusoidal fre-
quency could be applied on OSCIN. The peak to
peak voltage of this signal can be reduced down
to 60mV.
In this mode the frequency selection via FSEL is
still active.
Suggested values of C1 and C2 are shown in the
following table:
Crystal
4.332MHz
8.664MHz
17.328MHz
C1
27pF
27pF
27pF
C2
47pF
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