TDA7330B Datasheet, PDF (4/9 Pages) STMicroelectronics – SINGLE CHIP RDS DEMODULATOR FILTER

TDA7330B
ELECTRICAL CHARACTERISTICS (continued)
Measure
A
B
C
f1 (KHz)
56.5
56
55.5
f2 (KHz)
57
57
57
f3 (KHz)
57.5
58
58.5
∆Ph max
<5°
<7.5°
<10°
Note(2): The 3th harmonic (57KHz) must be less than -40dB in respect to the input signal 19KHz plus gain.
Figure 2: RDS timing diagram
OUTPUT TIMING
The generated 1187.5Hz output clock (RDCL
line) is synchronized to the incoming data.
According to the internal PLL lock condition this
Figure 3: Test Circuit
data change can results on the falling or on the
rising clock edge.
Whichever clock edge is used by the decoder (ris-
ing or falling edge) the data will remain valid for
416.7 µsec after the clock transition.
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