TDA7326 Datasheet, PDF (4/16 Pages) STMicroelectronics – AM-FM RADIO FREQUENCY SYNTHESIZER

TDA7326
ELECTRICAL CHARACTERISTICS (continued)
LOOP FILTER OUTPUT (LPOUT = PIN 14)
Symbol
Parameter
Test Condition
Min. Typ. Max. Unit
vOL
Output Voltage Low
ILOAD = 0.2mA VDD2; = 10V
0.5
0.8
V
VOH
Output Voltage High
-ILOAD = 0.2mA VDD2; = 10V
9
9.5
V
CHARGE PUMP CURRENT GENERATION (LPIN1, LPIN2 = PIN 15, 16)
Isi
Sink Current LPIN1,2
-Iso
Source Current LPIN1,2
DOUT1 OPENDRAIN OUTPUT(PIN 9)
CURR1 = 0, CURR2 = 0
CURR1 = 0, CURR2 = 1
CURR1 = 1, CURR2 = 1
CURR1 = 1, CURR2 = 0
CURR1 = 0, CURR2 = 0
CURR1 = 0, CURR2 = 1
CURR1 = 1, CURR2 = 1
CURR1 = 1, CURR2 = 0
2
5
7
µA
120 200 280
µA
180 300 420
µA
370 500 630
µA
2
5
7
µA
120 200 280
µA
180 300 420
µA
370 500 630
µA
vOL
Output Voltage Low
BUS INTERFACE
ILOAD = 1mA
0.2
0.5
V
-IIL
Input Leakage Current
VIN = VSS
-1
0.1
1
µA
IIH
Input Leakage Current
VIN = VSS
-1
0.1
1
µA
vIH
Input Voltage High
Leading edge
3.4
4.0
V
VIL
Input Voltage Low
Leading edge
1.0
1.6
V
BUS INTERFACE, WAITING TIME (see fig. 5) The Data is Acquired at the High → Low Clock Transition
t1
CLK Low to DLEN L → H
0.2
µs
t3
DATA Transition to CLK H → L
0.1
µs
t5
CLK H → L to DATA Transition
0.4
µs
BUS INTERFACE, DATA REPETITION TIME (see fig. 5)
tr1
Release Time Between 2 bytes,
except byte 4
tr2
Release Time after the
transmission of byte 4
FM mode
AM mode
BUS INTERFACE, SETUP TIME (see fig. 5)
5
µs
180
µs
2
ms
t2
DLEN High to CLK L → H
BUS INTERFACE, HOLD TIME (see fig. 5)
0.1
µs
t4
DATA Transition to CKL L → H
t6
CLK H → L to DLEN H → L
fCLK
CLK Frequency
Duty Cycle
tpl
Clock Pulse Low
tp h
Clock Pulse High
0
µs
0.4
µs
500 KHz
50
%
1
µs
1
µs
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