STD75N3LLH6 Datasheet, PDF (4/21 Pages) STMicroelectronics – N-channel 30 V, 0.0042 Ω, 75 A, DPAK, TO-220, IPAK, Short IPAK

Electrical characteristics
2
Electrical characteristics
STD/P/U75N3LLH6, STU75N3LLH6-S
(T_CASE=25°C unless otherwise specified)
Table 4. On/off states
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
Drain-source
V_{(BR)DSS breakdown voltage (VGS = 0)} I_D = 250 µA
Zero gate voltage
I_{DSS drain current (VGS = 0)}
V_DS = 30 V
V_DS =30 V T_C = 125 °C
I_GSS
Gate-body leakage
current (V_DS = 0)
V_GS = ± 20 V
V_GS(th) Gate threshold voltage
V_DS = V_GS, I_D = 250 µA
V_GS = 10 V, I_D = 37.5 A
SMD version
30
V
1
µA
10 µA
±100 nA
1
1.7
2.5
V
0.0042 0.0055 Ω
R_DS(on)
Static drain-source on
resistance
V_GS = 10 V, I_D = 37.5 A
V_GS = 4.5 V, I_D = 37.5 A
SMD version
0.0046 0.0059 Ω
0.0065 0.008 Ω
V_GS = 4.5 V, I_D = 37.5 A
0.0069 0.0084 Ω
Table 5.
Symbol
Dynamic
Parameter
Test conditions
Min. Typ. Max. Unit
C_iss
C_oss
C_rss
Input capacitance
Output capacitance
Reverse transfer
capacitance
1350 1690 2030 pF
V_DS = 25 V, f = 1 MHz,
230
290
350
pF
V_GS = 0
140 176 210 pF
Q_g
Q_gs
Q_gd
Q_gs1
Q_gs2
Total gate charge
Gate-source charge
Gate-drain charge
Pre V_th gate-to-source
charge
Post V_th gate-to-source
charge
V_DD = 15 V, I_D = 75 A,
V_GS = 4.5 V
(see Figure 14)
V_DD=15 V, I_D = 75 A
V_GS =5 V
(Figure 19)
17 23.8 nC
8
11.2 nC
6
8.4 nC
3.9 5.5 nC
4.1 5.7 nC
f=1 MHz gate bias
R_G Gate input resistance
Bias=0 test signal
1.25 1.7
2
Ω
level=20 mV open drain
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Doc ID 15978 Rev 4