STD60N3LH5_09 Datasheet, PDF (4/16 Pages) STMicroelectronics – N-channel 30 V, 0.0072 Ω, 48 A DPAK, IPAK, TO-220 STripFET™ V Power MOSFET

Electrical characteristics
STD60N3LH5, STP60N3LH5, STU60N3LH5
2
Electrical characteristics
(T_CASE = 25 °C unless otherwise specified)
Table 4. Static
Symbol
Parameter
V_(BR)DSS
Drain-source breakdown
Voltage
I_DSS
I_GSS
V_GS(th)
Zero gate voltage drain
current (V_GS = 0)
Gate body leakage current
(V_DS = 0)
Gate threshold voltage
R_DS(on)
Static drain-source on
resistance
Test conditions
I_D = 250 µA, V_GS= 0
V_DS = 30 V
V_DS = 30 V,Tc = 125 °C
V_GS = ± 22 V
V_DS= V_GS, I_D = 250 µA
V_GS= 10 V, I_D= 24 A
SMD version
V_GS= 10 V, I_D= 24 A
V_GS= 5 V, I_D= 24 A
SMD version
V_GS= 5 V, I_D= 24 A
Min. Typ. Max. Unit
30
V
1 µA
10 µA
±100 nA
1
1.8
3
V
0.0072 0.008 Ω
0.0076 0.0084 Ω
0.0088 0.011 Ω
0.0092 0.0114 Ω
Table 5. Dynamic
Symbol
Parameter
C_iss
C_oss
C_rss
Q_g
Q_gs
Q_gd
Q_gs1
Q_gs2
Input capacitance
Output capacitance
Reverse transfer
capacitance
Total gate charge
Gate-source charge
Gate-drain charge
Pre V_th gate-to-source
charge
Post V_th gate-to-source
charge
R_G Gate input resistance
Test conditions
V_DS =25 V, f=1 MHz,
V_GS=0
V_DD=15 V, I_D = 48 A
V_GS =5 V
(Figure 14)
V_DD=15 V, I_D = 48 A
V_GS =5 V
(Figure 19)
f=1 MHz gate bias
Bias= 0 test signal
level=20 mV
open drain
Min. Typ. Max. Unit
1350
pF
-
265
- pF
32
pF
8.8
nC
-
4.7
- nC
2.2
nC
2.2
nC
-
-
2.5
nC
-
1.1
-
Ω
4/16
Doc ID 14079 Rev 3