SRK2000A Datasheet, PDF (4/19 Pages) STMicroelectronics – Matched turn-off thresholds

Pin description
2
Pin description
Figure 2. Pin configuration
SRK2000A
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Table 2. Pin description
No. Name
Function
Signal ground. Return of the bias current of the device and 0 V reference for
1
SGND drain-to-source voltage monitors of both sections. Route this pin directly to
PGND.
Drain voltage threshold setting for synchronous rectifier MOSFET turn-off.
UVLO threshold programming. This pin is typically biased by either a pull-up
2
EN resistor connected to V_CC or by a resistor divider sensing V_CC. Pulling the pin to
ground disables the gate driver outputs GD1 and GD2 and can therefore be
used also as Enable input.
Drain voltage sensing for sections 1 and 2. These pins are to be connected to
the respective drain terminals of the corresponding synchronous rectifier
3
4
DVS1
DVS2
MOSFET via limiting resistors. When the voltage on either pin goes negative,
the corresponding synchronous rectifier MOSFET is switched on; as its
(negative) voltage exceeds a threshold defined by the EN pin, the MOSFET is
switched off. An internal logic rejects switching noise, however, extreme care in
the proper routing of the drain connection is recommended.
Gate driver output for sections 2 and 1. Each totem pole output stage is able to
5
GD2 _{drive the Power MOSFETs with a peak current of 1 A source and 3.5 A sink. The}
7
GD1 ^{high-level voltage of these pins is clamped at about 12 V to avoid excessive gate}
voltages in case the device is supplied with a high V_CC.
Power ground. Return for gate drive currents. Route this pin to the common
6
PGND point where the source terminals of both synchronous rectifier MOSFETs are
connected.
Supply voltage of the device. A small bypass capacitor (0.1 µF typ.) to SGND,
located as close to the IC’s pins as possible, may be useful to obtain a clean
8
V_CC supply voltage for the internal control circuitry. A similar bypass capacitor to
PGND, again located as close to the IC’s pins as possible, may be an effective
energy buffer for the pulsed gate drive currents.
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