PSD835G2 Datasheet, PDF (4/110 Pages) STMicroelectronics – Configurable Memory System on a Chip for 8-Bit Microcontrollers

PSD835G2
2.0
Key Features
PSD8XX Family
t A simple interface to 8-bit microcontrollers that use either multiplexed or
non-multiplexed busses. The bus interface logic uses the control signals generated by
the microcontroller automatically when the address is decoded and a read or write is
performed. A partial list of the MCU families supported include:
• Intel 8031, 80196, 80188, 80C251
• Motorola 68HC11 and 68HC16
• Philips 8031 and 80C51XA
• Zilog Z80, Z8 and Z180
• Infineon C500 family
t 4 Mbit Flash memory. This is the main Flash memory. It is divided into eight
equal-sized blocks that can be accessed with user-specified addresses.
t Internal secondary 256 Kbit Flash boot memory. It is divided into four equal-sized
blocks that can be accessed with user-specified addresses. This secondary memory
brings the ability to execute code and update the main Flash concurrently.
t 64 Kbit SRAM. The SRAM’s contents can be protected from a power failure by
connecting an external battery.
t CPLD with 16 Output Micro⇔Cells (OMCs) and 24 Input Micro⇔Cells (IMCs). The
CPLD may be used to efficiently implement a variety of logic functions for internal
and external control. Examples include state machines, loadable shift registers, and
loadable counters. The CPLD can also generate eight external chip selects.
t Decode PLD (DPLD) that decodes address for selection of internal memory blocks.
t 52 individually configurable I/O port pins that can be used for the following functions:
• MCU I/Os
• PLD I/Os
• Latched MCU address output
• Special function I/Os.
• I/O ports may be configured as open-drain outputs.
t Standby current as low as 50 µA for 5 V devices.
t Built-in JTAG compliant serial port allows full-chip In-System Programmability (ISP).
With it, you can program a blank device or reprogram a device in the factory or the field.
t Internal page register that can be used to expand the microcontroller address space
by a factor of 256.
t Internal programmable Power Management Unit (PMU) that supports a low power
mode called Power Down Mode. The PMU can automatically detect a lack of
microcontroller activity and put the PSD8XX into Power Down Mode.
t Erase/Write cycles:
• Flash memory – 100,000 minimum
• PLD – 1,000 minimum
3.0 PSD8XX
Series
Table 1. PSD8XX Product Matrix
Part #
PSD8XX
Series
Device
Flash
Flash
Main
Boot
Serial ISP Memory Memory
I/O PLD Input
Output PLD JTAG/ISP Kbit
Kbit
SRAM
Pins Inputs Macrocells Macrocells Outputs Port 8 Sectors (4 Sectors) Kbit
PSD835G2 52
24
16
24
Yes
4096
256
64
PSD8XX PSD813F2
27 57
24
16
19
Yes
1024
256
16
PSD834F2
27 57
24
16
19
Yes
2048
256
64
PSD833F2
27 57
24
16
19
Yes
1024
256
64
Supply
Voltage
5V
5V
5V
5V
3