P01 Datasheet, PDF (4/6 Pages) STMicroelectronics – 0.8A SCRs

P01 Series
Fig. 4: Relative variation of gate trigger current,
holding current and latching current versus
junction temperature (typical values).
IGT, IH, IL[Tj] / IGT, IH, IL[T] = 25°C
6
5
4
3
2
1
0
-40 -20
Tj(°C)
0 20 40 60
80 100 120 140
Fig. 5:Relative variation of holding current versus
gate-cathode resistance (typical values).
IH[Rgk]/IH[Rgk=1kΩ]
Rgk(kΩ)
Fig. 6: Relative variation of dV/dt immunity
versus gate-cathode resistance (typical values).
dV/dt[Rgk] / dV/dt[Rgk=1kΩ]
10.0
1.0
Rgk(kΩ)
0.1
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Fig. 8: Surge peak on-state current versus
number of cycles.
Fig. 7: Relative variation of dV/dt immunity
versus gate-cathode capacitance (typical values).
dV/dt[Cgk] / dV/dt[Rgk=1kΩ]
10
8
6
4
2
Cgk(nF)
0
0
1
2
3
4
5
6
7
Fig. 9: Non-repetitive surge peak on-state
current for a sinusoidal pulse with width
tp < 10 ms, and corresponding value of I²t.
ITSM(A)
8
7
6
5
Non repetitive
Tj initial=25°C
4
3
Repetitive
Tamb=25°C
2
1
0
1
10
tp=10ms
Onecycle
Numberofcycles
100
1000
ITSM(A), I²t(A²s)
100.0
10.0
1.0
0.1
0.01
tp(ms)
0.10
1.00
10.00
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